Document
NJU26041 Series
NJU26041 Series Data Sheet
■ General Description
The NJU26041 Series a Digital Signal Processor with built-in OTP (One Time Programmable). By the DSP with built-in OTP, customization is possible from various sound technology. The NJU26041 Series is suitable for TV, mini-component, speakers system and other audio products. This DSP can constitute a small system by combining a CODEC.
■ Package
NJU26041V
■ FEATURES
• 24bit Fixed-point Digital Signal Processing • System Clock Frequency : Maximum 38MHz • Digital Audio Interface : 3 Input ports / 3Output ports • Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs • Master / Slave Mode : In Master mode, MCK : 768/384/256fs • Serial Host Interface : I2C bus (Standard-mode/100kbps, First-mode/400kbps) : 4-Wire Serial bus (Clock, Enable, Input data, Output data) • Power Supply : 3.3 V • Input terminal : 5.0V Input tolerant • Package : SSOP32 ( Pb-Free )
■ Block Diagram
A D 1 /S D IN A D 2 /S S b S E R IA L A U D IO IN T E R F A C E BCKO PROGRAM CONTROL 2 4 -B IT x 2 4 -B IT M U L T IP L IE R ALU RESETb MCK CLK O U T CLK LRI T IM IN G GENERATOR A D D R E S S G E N E R A T I O N U N IT LRO SDO0 SDI [2 :0 ] SDO1 SDO2 BCKI S C L /S C K 2 4 b it F ix e d -p o in t D S P C o re S E R IA L HOST IN T E R F A C E
S D A /S D O U T
DATA RAM
F IR M W A R E O T P /R A M
G P IO 3 G e n e r a l I/O IN T E R F A C E G P IO 2 G P IO 1 G P IO 0
Fig.1 NJU26041 Hardware Block Diagram
Ver.2007-09-20
-1-
NJU26041 Series ■ Pin Configuration
VDD SDA / SDOUT SCL / SCK AD1 / SDIN AD2 / SSb RESETb VDD VDD VSS CLKOUT CLK SDI2 SDI1 SDI0 LRI BCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS TEST TEST GPIO0 GPIO1 GPIO2 GPIO3 / TEST VDD VSS TEST MCK SDO2 SDO1 SDO0 LRO BCKO
Fig. 2 Pin Configuration
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Ver.2007-09-20
NJU26041 Series ■ Pin Description
Table 1 Pin Description Pin No. Symbol 1, 7, 8, 25 VDD 2 3 4 5 6 9, 24, 32 10 11 12 13 14 15 16 17 18 19 20 21 22 23, 30, 31 26 27 28 29 Note : I IO OD I/O+ I/O SDA / SDOUT I/O Description
SCL / SCK AD1 / SDIN AD2 / SSb RESETb VSS CLKOUT CLK SDI2 SDI1 SDI0 LRI BCKI BCKO LRO SDO0 SDO1 SDO2 MCK TEST GPIO3/ TEST GPIO2 GPIO1 GPIO0 : Input : Input (Pull-down) : Output : Bi-directional (Open Drain) This pin requires a pull-up resistance. : Bi-directional (with Pull-up resistance) : Bi-directional (with Pull-down resistance)
Power Supply +3.3V / 4-Wire Serial Output I2C I/O This pin requires a pull-up resistance in both I2C bus and 4-Wire OD serial mode. 2 I I C Clock / Serial Clock I I2C Address / Serial Input I I2C Address / Serial Enable I Reset (RESETb=’Low’ : DSP Reset) GND O OSC Output I OSC Clock Input I Audio Data Input 2 I Audio Data Input 1 I Audio Data Input 0 I LR Clock Input I Bit Clock Input O Bit Clock Output O LR Clock Output O Audio Data Output 0 O Audio Data Output 1 O Audio Data Output 2 O Master Clock Output for A/D, D/A Ifor Test (connected to VSS) I/O + General Purpose IO 3 / for Test (Not connected : OPEN ) I/O - General Purpose IO 2 I/O - General Purpose IO 1 I/O - General Purpose IO 0
Ver.2007-09-20
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NJU26041 Series ■
Absolute Maximum Ratings
( VSS=0V=GND, Ta=25°C ) Rating Units
Table 2 Absolute Maximum Ratings Parameter Symbol Supply Voltage In, OD I/O Pin Voltage * Out CLK CLKOUT Power Dissipation Operating Voltage Storage Temperature VDD Vx(IN),Vx(OD) Vx(I/O) Vx(OUT) Vx(CLK) Vx(CLKOUT)
-0.3 to 3.8 -0.3 to 5.5 (VDD ≥ 3.0V) -0.3 to 3.8 (VDD < 3.0V) -0.3 to 3.8 -0.3 to 3.8 -0.3 to 3.8 -0.3 to 3.8
V
V
500 mW PD -40 to 85 TOPR °C TSTR -40 to 125 °C * The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent damage to the LSI. * Vx(IN) : 3, 4, 5, 6, 12,13,14,15,16, 23, 30, 31 pin * Vx(OD) : 2 pin * Vx(I/O) : 26, 27, 28, 29 pin * Vx(OUT) : 17, 18, 19, 20, 21, 22 pin * Vx(CLK) : 11 pin * Vx(CLKOUT) : 10 pin
■ Terminal equivalent circuit diagram
VDD RPU PAD RPD VSS Input, I/O (Input part) (With RPU: 26 pin )
(With RPD : 23, 27 to 31pin )
CLK CLKOUT
VDD
VSS CLK / CLKOUT
(No.10, 11 pin)
VDD PAD
Output Disable
VSS
Output, I/O ( Output part )
(No.2pin: Open Drain Output) Fig.3 NJU26041 Terminal equivalent circuit diagram
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Ver.2007-09-20
NJU26041 Series ■ Electric Characteristics
Table 3 Electric Characteristics
Parameter Operating Voltage Operating Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Symbol VDD IDD VIH VIL VOH VOL IIN Leakage Current
*4
( VDD=3.3V, fOSC=36.864MHz, Ta=25°C ) Test Condition VDD pin VDD=3.3V
*1
Min. 3.0 VDD x 0.7 0
Typ. 3.3 42 36.864 50
Max. 3.6 VDD
*2
Units V mA
VDD x 0.3 VDD VDD x 0.2 10 10 100 100 38 55
IOH= -1mA IOL= 1mA
*3
V
VDD x 0.8 0 -10
IIN(PU) II(PD)N
VIN = VSS to VDD
-100 -10 -
µA
Input Transition Time Clock Frequency Clock Duty Cycle
*5
tr / tf fOSC rEC No.11pin (CLK) No.11pin (CLK)
*6
ns MHz %
20 45
*1 Current of operation is at the starting time. It is.