HD74HC294

HD74HC292/HD74HC294 Programmable Frequency Divider/Digital Timer Description This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate incoming inspections. Test Point output is provided with HD74HC294 to facilitate incoming inspections. Features High Speed Operation: tpd (Clock to Q) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table CLR L H H H H L H X X H CLK1 X CLK2 X L Q Output Mode Cleared to L Count Count Inhibit Inhibit HD74HC292/HD74HC294 HD74HC292 Programming Inputs Frequency Division Q Out TP1 TP2 TP3 Binary Decimal Inhibit Inhibit 2 2 2 2 2 2 24 24 24 24 24 24 2 2 4 4 6 6 8 8 E L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H D C B A Binary Decimal L L L L L L L L L L L H Inhibit Inhibit 2 2 2 3 4 5 6 7 8 9 Binary Decimal Binary Decimal Inhibit Inhibit 4 8 16 32 64 128 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 Inhibit Inhibit 2 2 2 2 2 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 Inhibit Inhibit 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512...