HD74HC166

HD74HC166 Parallel-load 8-bit Shift Register Description This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Features High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Parallel Clear L H H H H H Shift/Load X X L H H X Clock Inhibit X L L L L H Clock X L Serial X X X H L X A ··· H X X a ··· h X X X Internal Outputs QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0 HD74HC166 Pin Arrangement Serial 1 Input A 2 B 3 Parallel Inputs C 4 D 5 Clock Inhibit 6 Clock 7 GND 8 (Top view) 16 VCC 15 Shift/Load Parallel 14 Input H 13 Output QH 12 G 11 F 10 E 9 Clear Parallel Inputs 2 HD74HC166 Logic Diagram Clear Clock Clock Inhibit Shift/ Load Serial Input D CK CK Q CLK A D B CK CK Q CLK D C D CK CK Q CLK D D CK CK Q CLK E D CK CK Q CLK F CK CK Q CLK ...