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HD74ACT166 Dataheets PDF



Part Number HD74ACT166
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description 8-bit Shift Register
Datasheet HD74ACT166 DatasheetHD74ACT166 Datasheet (PDF)

HD74AC166/HD74ACT166 8-bit Shift Register Description The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other. Features • Outputs Source/Sink 24 mA • .

  HD74ACT166   HD74ACT166


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HD74AC166/HD74ACT166 8-bit Shift Register Description The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other. Features • Outputs Source/Sink 24 mA • HD74ACT166 has TTL-Compatible Inputs Pin Arrangement DS 1 P0 2 P1 3 P2 4 P3 5 CP2 6 CP1 7 GND 8 (Top view) 16 VCC 15 PE 14 P7 13 Q7 12 P6 11 P5 10 P4 9 MR HD74AC166/HD74ACT166 Logic Symbol 15 2 3 4 5 10 11 12 14 PE P0 P1 P2 P3 P4 P5 P6 P7 1 7 6 1 2 DS CP MR Q7 9 13 VCC=Pin16 GND=Pin8 Pin Names CP1, CP2 DS PE P 0 to P7 MR Q7 Clock Pulse Inputs (Active Rising Edge) Serial Data Input Parallel Enable Input (Active Low) Parallel Data Inputs Asynchronous Master Reset Input (Active Low) Last Stage Output Functional Description Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should attain the High state while the other clock is still in the High state following the previous operation. When the Parallel Enable ( PE ) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 → Q1, Q1 → Q2, etc.) on the rising edge of the clock. 2 HD74AC166/HD74ACT166 Truth Table Inputs Parallel MR L H H H H H H : L : X : : PE X X L H H X CP 2 X L L L L H CP 1 X L DS X X X H L X P0 to P7 X X a ··· h X X X Internal Outputs Q0 L QA0 a H L QA0 Q6 L QB0 b QAn QAn QB0 Output Q7 L QH0 h QGn QGn QH0 High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Logic Diagram P0 DS P1 P2 P3 P4 P5 P6 MR P7 PE CP 1 2 R CP S CD Q R CP S CD Q Q7 3 HD74AC166/HD74ACT166 DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Maximum additional ICC/input (HD74ACT166) Symbol I CC I CC I CCT Max 80 8.0 1.5 Unit µA µA mA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case AC Characteristics: HD74AC166 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP 1 or CP2 to Q 7 Propagation delay CP 1 or CP2 to Q 7 Propagation delay MR to Q 7 Note: t PHL t PHL t PLH Symbol f max VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min 75 100 1.0 1.0 1.0 1.0 1.0 1.0 Typ — — 11.0 9.5 10.5 9.0 9.5 6.5 Max — — 14.5 11.5 14.0 11.0 12.0 9.0 Ta = –40°C to +85°C CL = 50 pF Min 65 80 1.0 1.0 1.0 1.0 1.0 1.0 Max — — 15.5 12.5 15.0 12.0 13.0 10.0 ns Unit MHz 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 4 HD74AC166/HD74ACT166 AC Operating Requirements: HD74AC166 Ta = +25°C CL = 50 pF Item Setup time PE or Pn or DS to CPn Hold time CP n to PE or Pn or DS Pulse width CP n or MR Recovery time MR to CPn Note: t rec tw th Symbol t su VCC (V)*1 Typ 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.0 2.0 –1.5 –0.5 2.0 2.0 –2.5 –1.5 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 4.0 3.0 3.0 5.5 4.5 0.0 0.0 6.0 4.5 3.0 3.0 7.0 5.0 0.0 0.0 Unit ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT166 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP n to Q 7 Propagation delay CP n to Q 7 Propagation delay MR to Q 7 Note: Symbol f max t PLH t PHL t PHL VCC (V)*1 5.0 5.0 5.0 5.0 Min 100 1.0 1.0 1.0 Typ — 10.0 9.5 8.5 Max — 12.5 12.0 11.0 Ta = –40°C to +85°C CL = 50 pF Min 80 1.0 1.0 1.0 Max — 13.5 13.0 12.0 Unit MHz ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC166/HD74ACT166 AC Operating Requirements: HD74ACT166 Ta = +25°C CL = 50 pF Item Setup time PE or Pn or DS to CPn Hold time CP n to PE or Pn or DS Pulse width CPn or MR Recovery time MR to CPn Note: Symbol t su th tw t rec VCC (V)*1 Typ 5.0 5.0 5.0 5.0 2.5 0.0 4.5 –2.5 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 7.0 1.5 7.0 0.5 8.0 1.5 8.0 0.5 Unit ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Symbol CIN CPD Typ 4.5 35.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V 6 19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 *0.22 ± 0.05 0.20 ± 0.04 8 0.80 Max 2.20 Max 0.20 7.80 + – 0.30 1.15 0° – 8° 0.70 ± 0.20 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.12 M Hitachi Code JEDEC E.


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