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HD74ACT112 Dataheets PDF



Part Number HD74ACT112
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description Dual JK Negative Edge-Triggered Flip-Flop
Datasheet HD74ACT112 DatasheetHD74ACT112 Datasheet (PDF)

HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the f.

  HD74ACT112   HD74ACT112


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HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features • Outputs Source/Sink 24 mA • HD74ACT112 has TTL-Compatible Inputs Pin Arrangement CP1 1 K1 2 J1 3 SD1 4 Q1 5 Q1 6 Q2 7 GND 8 (Top view) 16 VCC 15 CD1 14 CD2 13 CP2 12 K2 11 J2 10 SD2 9 Q2 HD74AC112/HD74ACT112 Logic Symbol 4 SD1 J1 CP1 K1 Q1 Q1 5 10 SD2 J2 CP2 K2 Q2 7 Q2 9 3 1 2 11 13 6 12 CD1 15 CD2 14 VCC = Pin16 GND = Pin8 Pin Names J1, J2, K1, K2 CP1, CP2 C D1, CD2 S D1, SD2 Q1, Q2, Q1, Q 2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active Low) Direct Set Inputs (Active Low) Outputs Asynchronous Inputs: Low input to SD sets Q to High level Low input to CD sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High 2 HD74AC112/HD74ACT112 Truth Table Inputs @tn J L L H H tn tn + 1 H L : : : : K L H L H Bit time before clock pulse. Bit time after clock pulse. High Voltage Level Low Voltage Level Outputs @tn + 1 Q Qn L H Qn Logic Diagram SD CD J K # CP CP # CP # CP CP CP CP #CP Q CP CP # CP Q DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Maximum additional ICC/input (HD74ACT112) Symbol I CC I CC I CCT Max 80 8.0 1.5 Unit µA µA mA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C VIN = VCC – 2.1 V, VCC = 5.5 V Ta = Worst case 3 HD74AC112/HD74ACT112 AC Characteristics: HD74AC112 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD, SD to Q or Q Propagation delay CD, SD to Q or Q Note: t PHL t PLH t PHL t PLH Symbol f max VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min 125 150 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ — — 11.0 8.5 11.0 8.5 9.5 7.0 11.5 9.0 Max — — 14.0 11.0 14.0 11.0 12.5 9.5 14.5 11.0 Ta = –40°C to +85°C CL = 50 pF Min 100 125 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max — — 15.0 12.0 15.0 12.0 13.5 10.5 15.5 12.5 ns Unit MHz 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74AC112 Ta = +25°C CL = 50 pF Item Setup time J or K to CP Hold time CP to J or K Pulse width CP or CD or SD Recovery time CD or SD to CP Note: t rec tw th Symbol t su VCC (V)*1 Typ 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.0 2.0 –1.5 –0.5 2.0 2.0 –1.0 –1.0 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 4.5 0.0 0.0 5.5 4.5 3.5 3.0 6.0 4.6 0.0 0.0 7.0 5.0 3.5 3.0 Unit ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 4 HD74AC112/HD74ACT112 AC Characteristics: HD74ACT112 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD, SD to Q or Q Propagation delay CD, SD to Q or Q Note: Symbol f max t PLH t PHL t PLH t PHL VCC (V)*1 5.0 5.0 5.0 5.0 5.0 Min 100 1.0 1.0 1.0 1.0 Typ — 10.5 10.5 8.0 10.5 Max — 13.0 13.0 10.0 12.5 Ta = –40°C to +85°C CL = 50 pF Min 80 1.0 1.0 1.0 1.0 Max — 14.0 14.0 11.0 13.5 Unit MHz ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74ACT112 Ta = +25°C CL = 50 pF Item Setup time J or K to CP Hold time CP to J or K Pulse width CP or CD or SD Recovery time CD , SD to CP Note: Symbol t su th tw t rec VCC (V)*1 Typ 5.0 5.0 5.0 5.0 2.5 0.0 4.5 –2.5 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 7.0 1.5 7.0 3.0 8.0 1.5 8.0 3.0 Unit ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Symbol CIN CPD Typ 4.5 35.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V 5 19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 *0.22 ± 0.05 0.20 ± 0.04 8 0.80 Max 2.20 Max 0.20 7.80 + – 0.30 1.15 0° – 8° 0.70 ± 0.20 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g *Dimension including the plating thickness Base material dimension 0.10 ± 0.10 0.15 Unit: mm 9.9 10.3 Max 16 9 3.95 1 1.27 0.635 Max 8 0.11 0.14 + – 0.04 1.75 Max *0.22 ± 0.03 0.20 ± 0.03 0.10 6.10 + – 0.30 1.08 0° – 8° 0.67 0.60 + – 0.20 *0.42 ± 0.08 0.40 ± 0.06 0.15 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms C.


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