Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to VCC or GND.
0 0 Registered/Active Low
0 1 Registered/Active High
1 0 Combinatorial/Active Low
1 1 Combinatorial/Active High
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
Registered Output Conﬁguration
Each macrocell of the PALCE22V10 includes a D-type ﬂip-ﬂop for data storage and
synchronization. The ﬂip-ﬂop is loaded on the LOW-to-HIGH transition of the clock input. In the
registered conﬁguration (S1 = 0), the array feedback is from Q of the ﬂip-ﬂop.
Combinatorial I/O Conﬁguration
Any macrocell can be conﬁgured as combinatorial by selecting the multiplexer path that bypasses
the ﬂip-ﬂop (S1 = 1). In the combinatorial conﬁguration, the feedback is from the pin.
PALCE22V10 and PALCE22V10Z Families