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HD74AC107 Dataheets PDF



Part Number HD74AC107
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description Dual JK Flip-Flop (with Separate Clear and Clock)
Datasheet HD74AC107 DatasheetHD74AC107 Datasheet (PDF)

HD74AC107/HD74ACT107 Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and.

  HD74AC107   HD74AC107


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HD74AC107/HD74ACT107 Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs; 4) transfer information from master to slave. Features • Outputs Source/Sink 24 mA • HD74ACT107 has TTL-Compatible Inputs Pin Arrangement J1 1 Q1 2 Q1 3 K1 4 Q2 5 Q2 6 GND 7 (Top view) 14 VCC 13 CD1 12 CP1 11 K2 10 CD2 9 CP2 8 J2 HD74AC107/HD74ACT107 Logic Symbol 3 8 9 Q1 2 11 1 12 4 J1 CP1 K1 Q1 J2 CP2 K2 Q2 6 CD1 13 CD2 10 Q2 5 VCC = Pin14 GND = Pin7 Pin Names J1, J2, K1, K2 CP1, CP2 C D1, CD2 Q1, Q2, Q1, Q 2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active Low) Outputs Truth Table Inputs @ tn J L L H H H L tn tn + 1 : : : : K L H L H High Voltage Level Low Voltage Level Bit time before clock pulse. Bit time after clock pulse. Outputs @ tn + 1 Q Qn L H Qn 2 HD74AC107/HD74ACT107 Logic Diagram CD J K CP #CP CP #CP Q #CP #CP Q CP CP CP CP CP DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Maximum additional ICC/input (HD74ACT107) Symbol I CC I CC I CCT Max 80 8.0 1.5 Unit µA µA mA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C VIN = VCC – 2.1 V, VCC = 5.5 V Ta = Worst case 3 HD74AC107/HD74ACT107 AC Characteristics: HD74AC107 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD to Q Propagation delay CD to Q Note: t PHL t PLH t PHL t PLH Symbol f max VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Min 125 150 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ — — 9.5 7.5 10.0 8.0 9.5 7.5 9.5 7.5 Max — — 13.0 10.0 13.5 10.5 13.0 10.0 13.0 10.0 Ta = –40°C to +85°C CL = 50 pF Min 100 125 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max — — 14.0 11.0 14.5 11.5 14.0 11.0 14.0 11.0 ns ns ns ns Unit MHz Operating Requirements: HD74AC107 Ta = +25°C CL = 50 pF Item Setup time J or k to CP Hold time CP to J or k Pulse width CP or CD Recovery time CD to CP Note: t rec tw th Symbol t su VCC (V)*1 Typ 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.0 2.0 –1.5 –0.5 2.0 2.0 –2.5 –1.5 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 4.0 0.0 0.0 5.5 4.5 0.0 0.0 6.0 4.5 0.0 0.0 7.5 5.0 0.0 0.0 Unit ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 4 HD74AC107/HD74ACT107 AC Characteristics: HD74ACT107 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD to Q Propagation delay CD to Q Note: Symbol f max t PLH t PHL t PLH t PHL VCC (V)*1 5.0 5.0 5.0 5.0 5.0 Min 100 1.0 1.0 1.0 1.0 Typ — 9.5 10.5 8.5 8.5 Max — 12.5 13.0 11.0 11.0 Ta = –40°C to +85°C CL = 50 pF Min 80 1.0 1.0 1.0 1.0 Max — 13.5 14.0 12.0 12.0 Unit MHz ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Operating Requirements: HD74ACT107 Ta = +25°C CL = 50 pF Item Setup time J or k to CP Hold time CP to J or k Pulse width CP or CD Recovery time CD to CP Note: Symbol t su th tw t rec VCC (V)*1 Typ 5.0 5.0 5.0 5.0 2.5 0.0 4.5 — Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 7.0 1.5 7.0 3.0 8.0 1.5 8.0 3.0 Unit ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Symbol CIN CPD Typ 4.5 35.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V 5 Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.70 ± 0.20 0.15 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g *Dimension including the plating thickness Base material dimension Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max 7 *0.20 ± 0.05 6.10 – 0.30 1.08 + 0.10 0.635 Max 0° – 8° 0.67 0.60 + – 0.20 1.27 *0.40 ± 0.06 0.11 0.14 + – 0.04 0.15 0.25 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g *Pd plating Unit: mm 5.00 5.30 Max 14 8 4.40 1 *0.22+0.08 –0.07 7 0.65 1.0 0.13 M 0.83 Max *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 6.40 ± 0.20 0° – 8° 0.50 ± 0.10 0.20 ± 0.06 0.10 0.07 +0.03 –0.04 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-14D — — 0.05 g Cautions 1. Hitachi neither warrants n.


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