Document
HD-6409
March 1997
CMOS Manchester Encoder-Decoder
Description
The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device manufactured using self-aligned silicon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Non return-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deficiencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link. In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This minimizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power. Manchester code is used in magnetic tape recording and in fiber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers.
Features
• Converter or Repeater Mode • Independent Manchester Encoder and Decoder Operation • Static to One Megabit/sec Data Rate Guaranteed • Low Bit Error Rate • Digital PLL Clock Recovery • On Chip Oscillator • Low Operating Power: 50mW Typical at +5V • Available in 20 Lead Dual-In-Line and 20 Pad LCC Package
Ordering Information
PACKAGE PDIP SOIC CERDIP DESC CLCC DESC TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -55oC to 125oC -40oC to +85oC -55oC to 125oC 1 MEGABIT/SEC HD3-6409-9 HD9P6409-9 HD1-6409-9 5962-9088801MRA HD4-6409-9 5962-9088801M2A PKG. NO. E20.3 M20.3 F20.3 F20.3 J20.A J20.A
Pinouts
HD-6409 (CERDIP, PDIP, SOIC) TOP VIEW HD-6409 (CLCC) TOP VIEW
BOO 19 18 BZO 17 SS 16 ECLK 15 CTS 14 MS 9 RST 10 GND 11 CO 12 IX 13 OX
BZI BOI UDI SD/CDS SDO SRST NVM DCLK RST
1 2 3 4 5 6 7 8 9
20 VCC 19 BOO 18 BZO 17 SS 16 ECLK 15 CTS 14 MS 13 OX 12 IX 11 CO NVM DCLK 7 8 SD/CDS SDO SRST 4 5 6
3
2
1
20
GND 10
VCC
BOI
UDI
BZI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2951.1
5-1
HD-6409 Block Diagram
SDO NVM BOI BZI UDI EDGE DETECTOR RST SD/CDS RESET SD INPUT/ OUTPUT SELECT MANCHESTER ENCODER COMMAND SYNC GENERATOR CTS DATA INPUT LOGIC 5-BIT SHIFT REGISTER AND DECODER OUTPUT SELECT LOGIC BOO BZO
SRST
MS IX OX CO SS OSCILLATOR ECLK DCLK
COUNTER CIRCUITS
Logic Symbol
SS CO
17 11
13 CLOCK GENERATOR 12
OX IX
SD/CDS ECLK
4 16 ENCODER
19 18 15
BOO BZO CTS
MS RST SDO DCLK NVM SRST
14 9 5 8 7 6
CONTROL 2 1 3 BOI BZI UDI
DECODER
5-2
HD-6409 Pin Description
PIN NUMBER 1 TYPE I SYMBOL BZl NAME Bipolar Zero Input DESCRIPTION Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low. In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). In the converter mode, a low o.