AD9652

Data Sheet 16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC) AD9652 FEATURES High dynamic range SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS) SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS) Noise spectral density (NSD) = −156.7 dBFS/Hz input noise at −1 dBFS at 70 MHz NSD = −157.6 dBFS/Hz for small signal at −7 dBFS at 70 MHz 90 dB channel isolation/crosstalk On-chip dithering (improves small signal linearity) Excellent IF sampling performance SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS) SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS) Full power bandwidth of 465 MHz On-chip 3.3 V buffer Programmable input span of 2 V p-p to 2.5 V p-p (default) Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz) Internal ADC clock duty cycle stabilizer SYNC input allows multichip synchronization Total power consumption: 2.16 W 3.3 V and 1.8 V supply voltages DDR LVDS (ANSI-644 levels) outputs Serial port control Energy saving power-down modes APPLICATIONS Military radar and communications Multimode digital receivers (3G or 4G) Test and instrumentation Smart antenna systems GENERAL DESCRIPTION The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-f...