Document
Low Skew, 1-to-6, Crystal/ LVCMOS/ Differential-to-3.3V, 2.5V LVPECL Fanout Buffer
ICS8536-01
DATA SHEET
GENERAL DESCRIPTION
The ICS8536-01 is a lo w skew, high performance 1-to-6 Selectable Crystal, Single-Ended, or Diff erential Input-to3.3V, 2.5V LVPECL Fanout Buffer. The ICS8536-01 has selectable cr ystal, single ended or diff erential clock inputs. The single ended cloc k input accepts LVCMOS or LVTTL input levels and tr anslates them to LVPECL levels. The CLK1, nCLK1 pair can accept most standard diff erential input levels. The output enable is inter nally synchronized to eliminate runt pulses on the outputs dur ing asynchronous assertion/deassertion of the cloc k enable pin. Guaranteed output and par t-to-part skew characteristics make the ICS8536-01 ideal f or those applications demanding well defined perf ormance and repeatability.
FEATURES
• Six 3.3V, 2.5V LVPECL outputs • Selectable crystal oscillator, differential CLK1, nCLK1 pair or LVCMOS/LVTTL clock input • CLK1, nCLK pair can accept the f ollowing differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Crystal frequency range: 12MHz - 40MHz • Output skew: 55ps (maximum) CLK1, nCLK1 @ 3.3V • Part-to-part skew: 450ps (maximum) • Additive phase jitter, RMS: 0.19ps (typical) • Full 3.3V or 2.5V supply mode • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) pac kages
BLOCK DIAGRAM
CLK_EN Pullup D Q CLK_SEL0 Pulldown CLK_SEL1 Pulldown LE
PIN ASSIGNMENT
nQ2 Q2 VCC nQ1 Q1 VEE nQ0 Q0 CLK_SEL0 XTAL_IN XTAL_OUT CLK_EN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 VCC Q4 nQ4 VCC Q5 nQ5 CLK_SEL1 nCLK1 CLK1 CLK0
XTAL_IN
Q0
OSC
XTAL_OUT CLK0 Pulldown CLK1 Pulldown nCLK1
Pullup
00 nQ0 6 LVPECL Outputs
01
ICS8536-01
Q5 nQ5
1X
24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View
ICS8536-01 REVISION B AUGUST 17, 2012
1
©2012 Integrated Device Technology, Inc.
http://www.Datasheet4U.com
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Ne umber 12 ,2 3V , 19, 22 41 ,5 6V 70 ,8 9, 16 10, 11 1N 2 10 3 11 4 11 5 15 7, 18 24 0, 21 23 3, 24 Ne am nt Q2, Q
CC
Tn yp O. utpu P. ower O. utpu P. ower O. upu In nput Input Ip npu In npu In npu Ip npu O. utpu O. utpu O. utpu Pullu P. ulldow P. ulldow P. ullu Pulldow
Descriptio Differential output pair. LVPECL interface levels Power supply pins Differential output pair. LVPECL interface levels Negative supply pin Differential output pair. LVPECL interface levels Clock select pins. LVCMOS/LVTTL interface levels. See Table 3B. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3A. LVCMOS/LVTTL clock input Non-inver ting differential clock input Inver ting differential clock input Differential output pair. LVPECL interface levels Differential output pair. LVPECL interface levels Differential output pair. LVPECL interface levels
nt Q1, Q
EE
nt Q0, Q CLK_SEL0, CLK_SEL1 XTAL_IN, XTAL_OUT Ct LK_E Ct LK Ct LK nt CLK nt Q5, Q nt Q4, Q nt Q3, Q
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol C IN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pulup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ
ICS8536AG-01 REVISION B AUGUST 17, 2012
2
©2012 Integrated Device Technology, Inc.
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs CLK_EN 0 0 0 1 1 CLK_SEL1 0 0 1 0 0 CLK_SEL0 0 1 X 0 1 Selected Source XTAL CLK0 CLK1, nCLK1 XTAL CLK0 Q0:Q5 Disabled Disabled Disabled Enabled Enabled Outputs nQ0:nQ5 Disabled Disabled Disabled Enabled Enabled
Enabled 1 1 X CLK1, nCLK1 Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the selected clock input as described in Table 3B.
Disabled
nCLK1 CLK0, CLK1, XTAL CLK_EN
Enabled
nQ0:nQ5 Q0:Q5
FIGURE 1. CLK_EN TIMING DIAGRAM
ICS8536AG-01 REVISION B AUGUST 17, 2012
3
©2012 Integrated Device Technology, Inc.
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, I O Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65°C to 150°C NOTE: Stresses be yond those listed under Absolute Maximum Ratings ma y cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or an y conditions be yond those listed in the DC Characteristics or AC Characteristics is not impl.