AK8185A

AK8185A Low - Jitter Clock Generator with Integrated VCO AK8185A -Preliminary- Features Low Phase Noise PLL RMS jitter 0.4ps typ. (12kHz to 20MHz) On chip VCO 4x Output Available Pin-Selectable LVPECL, LVDS, or 2-LVCMOS LVCMOS Bypass Output Available 3.3V for Core Operating Temperature Range: -40 to +85℃ Pin Package: 5mm x 5mm 32-pin Leadless QFN (Pb-free) - Description AK8185A is a Low – Jitter Clock Generator with sub pico-second jitter performance. Also Low power consumption is the advantage for advanced optimized application. - Application Ethernet SONET Fibre Channel SAN Cost-Effective High-Frequency Crystal Oscillator Replacement - Block Diagram Vcc_IN Input Frequency Range: 21.875MHz-28.47MHz XIN XO / LVCMOS Phase Frequency Detector Charge Pump Loop Filter Vcc_PLL1 Vcc_PLL2 Vcc_VCO Vcc_VDD Vcc_OUT LVCMOS Output Frequency Range: 43.75MHz-683.264MHz LVPECL LVCMOS LVDS LVPECL LVCMOS LVDS LVPECL LVCMOS LVDS LVPECL LVCMOS LVDS Output Driver OS[1...0] +15 +3 +20 VCO +24 +5 +25 Feedback Divider Prescaler Divider +4 +1 . . . +4 +6 +8 Output Divider RSTN PR[1...0] OD[2...0] Fig. 1 draft-E-02 -1- Dec. 2012 http://www.Datasheet4U.com AK8185A - Pin Assignments (Top view) 30 VCC_OUT 27 VCC_OUT 31 OUTN2 28 OUTN3 OUTP2 OUTP3 PR1 32 29 26 VCC_OUT 1 25 PR0 24 NC OUTN1 2 23 OSC_OUT OUTP1 3 AK8185A 22 21 GND1 XIN VCC_OUT 4 OUTN0 5 6 Thermal Pad (must be soldered to ground) 20 VCC_IN 19 REG_CAP1 OUTP0 CE 7 8 18 VCC_PLL1 17 REG_CAP2 NC 10 11...