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CY7C1049 Dataheets PDF



Part Number CY7C1049
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 512K x 8 Static RAM
Datasheet CY7C1049 DatasheetCY7C1049 Datasheet (PDF)

049 PRELIMINARY CY7C1049 512K x 8 Static RAM Features • High speed —t AA = 15 ns • Low active power — 1210 mW (max.) • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished.

  CY7C1049   CY7C1049



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049 PRELIMINARY CY7C1049 512K x 8 Static RAM Features • High speed —t AA = 15 ns • Low active power — 1210 mW (max.) • Low CMOS standby power (Commercial L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state w hen the de vice is de selected (C E HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049 is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Functional Description The CY7C1049 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 ARRAY I/O3 I/O4 I/O5 1049–2 CE WE COLUMN DECODER POWER DOWN I/O6 I/O7 A 11 A 12 A 13 A14 A15 A16 A17 A18 OE 1049–1 Selection Guide 7C1049-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com’l Com’l Ind’l Military Shaded areas contain advance information. 7C1049-15 15 220 8 0.5 9 7C1049-17 17 195 8 0.5 9 7C1049-20 20 185 8 0.5 9 10 7C1049-25 25 180 8 0.5 9 10 12 240 8 L 0.5 9 Cypress Semiconductor Corporation Document #: 38-05063 Rev. ** • 3901 North First Street • San Jose • CA 951 34 • 408-943-2600 Revised August 31, 2001 http://www.Datasheet4U.com PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW) ..........................


39VF010 CY7C1049 2SC787


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