VG36641641DT

VIS Description 4 (word x bit x bank), respectively. VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII. Features Single 3.3V ( ± 0.3V ) power supply High speed clock cycle time -6 : 166MHz<3-3-3>, available only on 4MX16 option -7 : 143MHz<3-3-3>, 133MHz<2-3-2> -7L: 133MHz<3-3-3> -8H: 100MHz<2-2-2> Fully synchronous operation referenced to clock rising edge Possible to assert random column access in every cycle Quad internal banks controlled by A12 & A13 (Bank Select) Byte control by LDQM and UDQM for VG36641641D Programmable Wrap sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable /CAS latency (2 and 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh X4, X8, X16 organization LVTTL compatible inputs and outputs 4,096 refresh cycles / 64ms Burst termination by Burst stop and Precharge command http://www.Datasheet4U.com Document :1G5-0177 Rev.2 Page 1 VIS Pin Configurations VG3664...