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2064VE Dataheets PDF



Part Number 2064VE
Manufacturers LatticeSemiconductor
Logo LatticeSemiconductor
Description 3.3VIn-SystemProgrammableHighDensitySuperFASTPLD
Datasheet 2064VE Datasheet2064VE Datasheet (PDF)

ispLSI 2064VE 3.3V In-System Programmable High Density SuperFAST™ PLD Features • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices • 3.3V LOW VOLTAGE 2064 ARCHITECTURE — Interfaces with Standard 5V .

  2064VE   2064VE



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ispLSI 2064VE 3.3V In-System Programmable High Density SuperFAST™ PLD Features • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices • 3.3V LOW VOLTAGE 2064 ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 280MHz* Maximum Operating Frequency — tpd = 3.5ns* Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms *Advanced Information Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ® Functional Block Diagram Input Bus Output Routing Pool (ORP) B7 B6 B5 B4 A0 Output Routing Pool (ORP) Input Bus A2 GLB Logic Array D Q D Q B1 D Q A3 A4 A5 A6 A7 B0 Output Routing Pool (ORP) Input Bus 0139A/2064V Description The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2064ve_06 1 Input Bus A1 D Q B2 Output Routing Pool (ORP) Global Routing Pool (GRP) B3 Specifications ispLSI 2064VE Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) GOE 0 GOE 1 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 I/O 31 I/O 30 I/O 29 I/O 28 Input Bus Generic Logic Blocks (GLBs) I/O 27 I/O 26 I/O 25 I/O 24 Input Bus Generic Logic Blocks (GLBs) Megablock B7 Output Routing Pool (ORP) B6 B5 B4 Megablock B7 Output Routing Pool (ORP) B6 B5 B4 Output Routing Pool (ORP) Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1 A2 B1 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 TCK/IN 3 TDO/IN 2 Input Bus A2 B1 A3 B0 I/O 4 I/O 5 I/O 6 I/O 7 TDI/IN 0 TDO/IN 1 Input Bus I/O 4 I/O 5 I/O 6 I/O 7 A1 Global Routing Pool (GRP) B2 I/O 43 I/O 42 I/O 41 I/O 40 A1 Global Routing Pool (GRP) B2 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 I/O 47 A0 B3 I/O 46 I/O 45 I/O 44 I/O 0 I/O 1 I/O 2 I/O 3 I/O 23 A0 B3 I/O 22 I/O 21 I/O 20 A3 B0 I/O 19 I/O 18 I/O 17 I/O 16 GOE0/IN 3 A4 A5 A6 A7 A4 A5 A6 A7 TMS/I.


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