PBL3796-2

April 1997 www.DataSheet4U.com PBL 3796, PBL 3796/2 Subscriber Line Interface Circuit Description PBL 3796 is an analog Subscriber Line Interface Circuits (SLICs), which are fabricated in a 75 V bipolar, monolithic process. The programmable battery feed is resistive with short-loop current limiting. A switch-mode regulator reduces on-chip power dissipation in the active state. In the standby state, power dissipation is further reduced, while still permitting supervisory functions to be active. Tip-ring polarity is reversible without altering SLIC supervisory and voice frequency (vf) functions. Tip and ring outputs can be set to high impedance states. These and other operating states are activated via a parallel, four bit control word. An external resistor controls the off-hook detector threshold current. The ring trip detector can operate with both balanced and unbalanced ringing systems. The two detectors are read via a shared output. Ring and test relay drivers with internal clamp diodes are provided. The complex or real two-wire impedance is set by a scaled, lumped element network. Two- to four-wire and four- to two-wire signal conversion is provided by the SLIC in conjunction with either a conventional or a programmable CODEC/filter. Longitudinal line voltages are suppressed by a control loop within the SLIC. Packages are 28-pin, dual-in-line; 32-pin or 44-pin j-leaded chip carrier. The difference between PBL 3796 and PBL 3796/2 is mainly the longitudinal balance spec. ...