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PHP12N50E Dataheets PDF



Part Number PHP12N50E
Manufacturers Philips
Logo Philips
Description PowerMOS transistors
Datasheet PHP12N50E DatasheetPHP12N50E Datasheet (PDF)

Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated FEATURES • Repetitive Avalanche Rated • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance PHB11N50E, PHW11N50E SYMBOL d QUICK REFERENCE DATA VDSS = 500 V g ID = 10.9 A RDS(ON) ≤ 0.55 Ω s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer m.

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Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated FEATURES • Repetitive Avalanche Rated • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance PHB11N50E, PHW11N50E SYMBOL d QUICK REFERENCE DATA VDSS = 500 V g ID = 10.9 A RDS(ON) ≤ 0.55 Ω s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The PHW11N50E is supplied in the SOT429 (TO247) conventional leaded package. The PHB11N50E is supplied in the SOT404 surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain1 source SOT404 tab SOT429 (TO247) 2 drain 1 3 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Operating junction and storage temperature range CONDITIONS Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 500 500 ± 30 10.9 6.9 44 156 150 UNIT V V V A A A W ˚C 1 It is not possible to make connection to pin 2 of the SOT404 package. December 1998 1 Rev 1.000 http://www.Datasheet4U.com Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS EAR IAS, IAR Non-repetitive avalanche energy CONDITIONS PHB11N50E, PHW11N50E MIN. - MAX. 707 18 10.9 UNIT mJ mJ A Unclamped inductive load, IAS = 10.9 A; tp = 0.2 ms; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V Repetitive avalanche energy2 IAR = 10.9 A; tp = 2.5 µs; Tj prior to avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V Repetitive and non-repetitive avalanche current THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT429 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT 60 45 50 0.8 K/W K/W K/W K/W ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage ∆V(BR)DSS / Drain-source breakdown ∆Tj voltage temperature coefficient Drain-source on resistance RDS(ON) VGS(TO) Gate threshold voltage gfs Forward transconductance Drain-source leakage current IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ld Ls Ciss Coss Crss V(BR)DSS CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA MIN. 500 2.0 4 TYP. MAX. UNIT 0.1 0.47 3.0 6.5 1 60 10 75 7 39 11 38 92 40 3.5 4.5 7.5 1326 182 96 0.55 4.0 25 500 200 100 12 55 V %/K Ω V S µA µA nA nC nC nC ns ns ns ns nH nH nH pF pF pF VGS = 10 V; ID = 5.5 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 5.5 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 ˚C Gate-source leakage current VGS = ±30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 11 A; VDD = 400 V; VGS = 10 V VDD = 250 V; RD = 22 Ω; RG = 5.6 Ω Measured from tab to centre of die Measured from drain lead to centre of die (SOT429 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz 2 pulse width and repetition rate limited by Tj max. December 1998 2 Rev 1.000 http://www.Datasheet4U.com Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHB11N50E, PHW11N50E SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25˚C Tmb = 25˚C IS = 11 A; VGS = 0 V IS = 11 A; VGS = 0 V; dI/dt = 100 A/µs MIN. TYP. MAX. UNIT 630 6.9 10.9 44 1.2 A A V ns µC December 1998 3 Rev 1.000 http://www.Datasheet4U.com Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHB11N50E, PHW11N50E 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating Transient Thermal Impedance, Zth j-a (K/W) PHP11N50E 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 P D Single pulse tp D = tp/T 0.01 T t 1E+00 1E+01 0 20 40 60 80 100 Tmb / C 120 140 0.001 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) ID% Normalised Current Derating Fig.4. T.


2SC4488 PHP12N50E PHW11N50E


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