Document
CYDXXS72V18 CYDXXS36V18 CYDXXS18V18
FullFlex™ Synchronous SDR Dual Port SRAM
FullFlex™ Synchronous SDR Dual Port SRAM
Features
■ ■
Functional Description
The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode. The advanced features include the following:
■
True dual port memory enables simultaneous access the shared array from each port Synchronous pipelined operation with single data rate (SDR) operation on each port ❐ SDR interface at 200 MHz ❐ Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports) Selectable pipelined or flow-through mode 1.5 V or 1.8 V core power supply Commercial and Industrial temperature IEEE 1149.1 JTAG boundary scan Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages FullFlex72 family ❐ 36-Mbit: 512 K × 72 (CYD36S72V18) ❐ 18-Mbit: 256 K × 72 (CYD18S72V18) ❐ 9-Mbit: 128 K × 72 (CYD09S72V18) FullFlex36 family ❐ 36-Mbit: 1 M × 36 (CYD36S36V18) ❐ 18-Mbit: 512 K × 36 (CYD18S36V18) ❐ 9-Mbit: 256 K × 36 (CYD09S36V18) ❐ 2-Mbit: 64 K × 36 (CYD02S36V18) FullFlex18 family ❐ 36-Mbit: 2 M × 18 (CYD36S18V18) ❐ 18-Mbit: 1 M × 18 (CYD18S18V18) ❐ 9-Mbit: 512 K × 18 (CYD09S18V18) Built in deterministic access control to manage address collisions ❐ Deterministic flag output upon collision detection ❐ Collision detection on back-to-back clock cycles ❐ First busy address readback Advanced features for improved high speed data transfer and flexibility ❐ Variable impedance matching (VIM) ❐ Echo clocks ❐ Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V), 1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port ❐ Burst counters for sequential memory access ❐ Mailbox with interrupt flags for message passing ❐ Dual chip enables for easy depth expansion
■ ■ ■ ■ ■ ■
Built in deterministic access control to manage address collisions during simultaneous access to the same memory location Variable impedance matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance Echo clocks to improve data transfer
■
■
■
To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles before a change in CE0 or CE1 enables or disables the databus matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port. Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally. Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt (CNTINT) flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset (MRST) are also available. The Logic Block Diagram on page 2 shows these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package except the 36-Mbit devices which are offered in 484-ball plastic BGA package.
■
■
■
Cypress Semiconductor Corporation Document Number: 38-06082 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600 Revised February 5, 2013
http://www.Datasheet4U.com
CYDXXS72V18 CYDXXS36V18 CYDXXS18V18
Logic Block Diagram
The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3]
FTSELL CQENL PORTSTD[1:0]L CONFIG Block CONFIG Block FTSELR CQENR PORTSTD[1:0]R
DQ[71:0]L BE [7:0]L CE0L CE1L OEL R/WL CQ1L CQ1L CQ0L CQ0L
IO Control
IO Control
DQ [71:0]R BE [7:0]R CE0R CE1R OER R/WR CQ1R CQ1R CQ0R CQ0R
Dual Port Array
BUSYL
Collision Detection Logic
BUSYR
A [20:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL WRPL
Address & Counter Logic
Address & Counter Logic
A [20:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR
Mailboxes INTL INTR JTAG
TRST TMS TDI TDO TCK
ZQ0L ZQ1L READYL LowSPDL
RESET LOGIC
ZQ0R ZQ1R MRST READYR LowSPDR
Notes 1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. T.