HIGH SPEEDFET-INPUTOP AMPS
The AD513 and AD516 high speedFET op amps combine
high DC accuracy with excellent dynamic response by utilizing
the flexibility of exrernal compensation. With simple lag com-
pensation, the AD513 and AD516 achieve slew rate of
20V/J.!Sec, and gain bandwidth of IMHz at unity. gain and
10MHz for gains greater than 100. With feedforward compen-
sation a.slew rate of 50VIJ.lSec and gain bandwidth of 30MHz
can be achieved. High accuracy DC specifications includernax
bias current as low as 20pA, a minimum gain of 50,000, and
CMRR of 80dB.
The AD513 is suggested for all general purpose FET input am-
plifier requirements where low cost and frequency response
flexibility are of prime importance. The AD516, with specifi-
cations otherwise similar to the AD513, offers significant im-
provement in offset voltage by supplementing the AD513
f:~confIgUration with internal laser trimming of thin fIlm re-
sistors to provide typical offset voltages below 1mV.
The devices are also fully shorr circuit protected and can be
exrernally offset voltage nulled. All the circuits are supplied in
Othe TO-99 package in the same pin configuration as the
ADI0IA and ADI081108A. The AD513J/AD516J and
BAD513K/AD516K are specified for 0 to +70°C temperature
Sr-a5~5e Cotpoer+a1ti2o5~; Ct.he AD513S/AD516S for operation from
Slew Rate (V/,us)
OELECTRICAL SPECIFICATIONS (Typical @ +25°C and.:t15VDC unless otherwise specified.)
EOpen Loop Gain (Note 1)
VOUT = !IOV, RL ?o2kQ
TA = min to nux
Voltage at RL = 2kQ. TA = min to nux
at RL = IOkn,TA =mintomax
Load Capacitance, Unity Gain (Note 2)
Short c.irclIit c.urtenr
Unity Gain, Small Signal (Fecdforward)
Slew Rate, Unity Gain (Fecdforward)
Input Offset Voltage (Note 3)
vs TemperatUre, T A = min to max
vs Supply, T A = min to nux
SOmV nux/3.5mV max
300p.V IV max
20mV maxll.SmV max
2Sp.V t" e max
20m V maxll.5mV
Input Bias Current
Either Input (Note 4)
Voltage, O.IHz to 10Hz
SHz to SOkHz
f = 1kHz (spot noise)
10' I QI12pl'
Input Volrage Range
Common Mode, T A = min to max
Common Mode Rejection. V;" = ~IOV
~(S to 18)V
0 to +70"e
-6S"e to +Iso"e
-S5"e to +125"e
I. Open Loop Gain is specified with Vos both nulled and unDulled.
.Specifications same as for ADS\3J.
2. A conservative design would not exceed S.oOpF of load capacitance.
3. Input Offset Voltage spe~ifications
are guaranteed after S minutes of operation at T A = +2SoC.
4. Bias Current specifications are guaranteed after S minutes of operation at T A = +2SoC. For
hi~er temperatUres, the current doubles every +IO"C.
152 LINEAR IC's
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