HY57V641620LTP

64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History Revision No. 0.1 History Initial Draft Draft Date Jan. 2007 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Jan. 2007 1 Free Datasheet http://www.0PDF.com Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620F(L/S)TP Series DESCRIPTION The Hynix HY57V641620F(L/S)TP series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620F(L/S)TP is organized as 4banks of 1,048,576x16. HY57V641620F(L/S)TP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write co...