Document
4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Feature
VDD = VDDQ = 1.5V ± 0.075V (JEDEC Standard Power Supply) VDD = VDDQ = 1.35V -0.0675V/+0.1V (Backward Compatible to VDD = VDDQ = 1.5V ±0.075V) 8 Internal memory banks (BA0- BA2) Differential clock input (CK, ) Programmable Latency: 5, 6, 7, 8, 9, 10, 11, 12, 13 WRITE Latency (CWL): 5,6,7,8,9, 10 POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2 clock Programmable Sequential / Interleave Burst Type Programmable Burst Length: 4, 8 Through ZQ pin (RZQ:240 ohm±1%) 8n-bit prefetch architecture Output Driver Impedance Control Differential bidirectional data strobe Internal(self) calibration:Internal self calibration OCD Calibration Dynamic ODT (Rtt_Nom & Rtt_WR) Auto Self-Refresh Self-Refresh Temperature RoHS compliance and Halogen free Packages: 78-Balls BGA for x4/x8 components 96-Ball BGA for x16 components
Description
The 4Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM. The 4Gb chip is organized as 128Mbit x 4 I/O x 8 bank , 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V and 1.35V -0.0675V/+0.1V power supply and are available in BGA packages.
1
REV 1.0
04/ 2012
Free Datasheet http://www.0PDF.com
4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Pin Configuration – 78 balls BGA Package (x4)
< TOP View>
See the balls through the package
x4 1 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 2 VDD VSSQ DQ2 NC VDDQ VSS VDD BA0 A3 A5 A7
3 NC DQ0 DQS NC BA2 A0 A2 A9 A13 A B C D E F G H J K L M N
7 NC DM DQ1 VDD NC CK A10/AP A15 A12/ A1 A11 A14
8 VSS VSSQ DQ3 VSS NC VSS VDD ZQ VERFCA BA1 A4 A6 A8
9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS
2
REV1.0
04/ 2012
Free Datasheet http://www.0PDF.com
4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Pin Configuration – 78 balls BGA Package (X8)
< TOP View>
See the balls through the package
x8 1 VSS 2 VDD 3 NC A 7 NU/ 8 VSS 9 VDD
VSS
VSSQ
DQ0
B
DM/TDQS
VSSQ
VDDQ
VDDQ
DQ2
DQS
C
DQ1
DQ3
VSSQ
VSSQ
DQ6
D
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
E
DQ7
DQ5
VDDQ
NC ODT
VSS
F
CK
VSS
NC
VDD
G
VDD
CKE
NC
H
A10/AP
ZQ
NC
VSS
BA0
BA2
J
A15
VERFCA
VSS
VDD
A3
A0
K
A12/
BA1
VDD
VSS
A 5
A2
L
A1
A4
VSS
VDD
A7
A9
M
A11
A6
VDD
VSS
A13
N
A14
A8
VSS
3
REV1.0
04/ 2012
Free Datasheet http://www.0PDF.com
4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Pin Configuration –
96 balls BGA Package (x16)
< TOP View>
See the balls through the package
x 16 1 VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD BA0 A3 A5 A7 3 DQU7 VSS DQU1 UDM DQL0 DQSL DQL4 BA2 A0 A2 A9 A13 A B C D E F G H J K L M N P R T 7 DQU4 DQSU DQU0 DML DQL1 VDD DQL7 CK A10/AP A15 A12/BC# A1 A11 A14 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS
4
REV1.0
04/ 2012
Free Datasheet http://www.0PDF.com
4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Input / Output Functional Description
Symbol CK, Type Input Function Clock: CK and are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of . Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has CKE Input become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this i.