HEF4029B

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4029B MSI Synchronous up/down counter, binary/decade counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Synchronous up/down counter, binary/decade counter DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel buffered outputs (O0 to O3) and an active LOW terminal count output (TC). HEF4029B MSI Information on P0 to P3 is asynchronously loaded into the counter while PL is HIGH, independent of CP. The counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the counter reaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW. Fig.1 Functional diagram. Fig.2 Pinning diagram. PINNING HEF4029BP(N): HEF4029BD(F): HEF4029BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PL P0 to P3 B...