Document
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK2341
SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE
DESCRIPTION
The 2SK2341 is N-channel Power MOS Field Effect Transistor designed for high voltage switching applications.
PACKAGE DIMENSIONS
(in millimeters)
10.0 ± 0.3 4.5 ± 0.2 2.7 ± 0.2
FEATURES
φ3.2 ± 0.2
• • •
Low On-state Resistance RDS(on) = 0.26 Ω MAX. (VGS = 10 V, ID = 6.0 A)
3 ± 0.1 1 2 3 4 ± 0.2
High Avalanche Capability Ratings
Drain to Source Voltage Gate to Source Voltage Drain Current (DC) Drain Current (pulse)
VDSS VGSS ID (DC) ID (pulse)*
250 ± 30 ± 11 ± 44 35 2.0 –55 to +150 150 11 320
V V A A W W °C °C A mJ
1 2 3 0.7 ± 0.1 2.54 TYP.
13.5 MIN. 0.65 ± 0.1
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Total Power Dissipation (TC = 25 °C) PT1 Total Power Dissipation (Ta = 25 °C) PT2 Storage Temperature Channel Temperature Single Avalanche Current Single Avalanche Energy
*PW ≤ 10 µs, Duty Cycle ≤ 1 % **Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0
1.3 ± 0.2 1.5 ± 0.2 2.54 TYP.
12.0 ± 0.2
LOW Ciss
Ciss = 1090 pF TYP.
15.0 ± 0.3
2.5 ± 0.1
Tstg Tch IAS** EAS**
1. Gate 2. Drain 3. Source
MP-45F(SIOLATED TO-220)
Drain (D)
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
Source (S) Gate (G) Body diode
Document No. TC-2511 (O.D. No. TC–8070) Date Published January 1995 P Printed in Japan
©
1995
Free Datasheet http://www.Datasheet-PDF.com/
2SK2341
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTIC Drain to Source On-state Resistance Gate to Source Cutoff Voltage Forward Transfer Admittance Drain Leakage Current Gate to Source Leakage Current Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge SYMBOL RDS(on) VGS(off) yfs IDSS IGSS Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr 1090 420 80 20 20 50 15 33 6.0 13 1.0 220 1.0 2.0 3.0 100 ± 100 MIN. TYP. 0.21 MAX. 0.26 4.0 UNIT Ω V S TEST CONDITIONS VGS = 10 V, ID = 6 A VDS = 10 V, ID = 1 mA VDS = 10 V, ID = 6 A VDS = 250V, VGS = 0 VGS = ± 30 V, VDS = 0 VDS = 10 V VGS = 0 f = 1 MHz VGS = 10 V VDD = 150 V ID = 6 A, RG = 10 Ω RL = 25 Ω VGS = 10 V ID = 11 A VDD = 200 V IF = 11 A, VGS = 0 1F = 11 A di/dt = 50 A/µs
µA
nA pF pF pF ns ns ns ns nC nC nC V ns
µC
Test Circuit 1 : Avalanche Capability
D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V 50 Ω
Test Circuit 2 : Switching Time
D.U.T.
L VDD PG. RG RG = 10 Ω
RL VGS VDD
Wave Form
VGS
0 10 % VGS (on) 90 %
ID
90 % 90 % ID 0 10 % td(on) ton tr td (off) toff 10 % tf
BVDSS IAS ID VDD VDS
VGS 0 τ τ = 1 µs Duty Cycle ≤ 1%
ID Wave Form
Starting Tch
Test Circuit 3 : Gate Charge
D.U.T. IG = 2 mA PG. 50 Ω
RL V.