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Free Datasheet http://www.datasheet4u.net/
ICS90C64
TABLE OF CONTENTS
Section Title
PREFACE 1.0 INTRODUCTION 1.1 Description 1.2 Features ICS90C64 VGA INTERFACE 2.1 System Bus Inputs 2.2 Inputs from VGA Controller 2.3 Outputs to VGA Controller 2.4 Analog Filters 2.5 User Definable Inputs 2.6 Power Considerations PIN DESCRIPTIONS . . .
Page
11-1 11-1 11-1 11-2 11-3 11-4 11-4 11-4 11-4 11-4 11-5 11-8 11-9 11-9 11-9 . 11-10 . 11-12
2.0
3.0 4.0
ABSOLUTE MAXIMUM RATINGS 4.1 Standard Test Conditions 4.2 D.C. Characteristics AC Timing Characteristics Packaging Information
5.0 6.0
II
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ICS90C64
LIST OF ILLUSTRATIONS
Figure
2-1 2-2 5-1 6-1
Title
ICS90C64 Interface ICS90C64 Functional Block Diagram ICS90C64 Timings . . . . . . . ICS90C64 20-Pin PLCC Package Dimensions Other ICS Package Dimensions . . . . . .
Page
· 11-3 · 11-7 · 11-11 · 11-12 · 11-13
6-2
LIST OF TABLES
Table
1-1 1-2 3-1 4-1 5-1
Title
VCLK Selection MCLK Selection Pin Descriptions D.C. Characteristics AC Timing Characteristics
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11-6 11-6 11-8 11-9 · 11-10
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11115191
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PREFACE
ICS90C64
PREFACE
The Integrated Circuit Systems ICS90C64 dual video/memory clock generator was designed exclusively to work with Western Digital video graphics chips. Because you get optimum video subsystem performance when you use this video/memory clock generator with the Western Digital video graphics chips, we have included the ICS90C64 in our databook. You can contact Integrated Circuit Systems at the following address:
Integrated Circuit Systems, Inc. Valley Forge Corporate Center 2626 Van Buren Ave., P.O. Box 968 Valley Forge, PA 19482 Phone: (215) 666-1900 Fax: (215) 666-1099
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ICS90C64V
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1.0
INTRODUCTION
20-PIN PLCC DIAGRAM
The Integrated Circuit Systems ICS90C64 is a dual clock generator for VGA applications. It simultaneously generates two clocks. One clock is forthe video memory, and the other is the video dot clock. This data sheet supplies sales order information, a functional overview, signal pin details, a block diagram, AC/DC characteristics, timing diagrams, and package mechanical information.
Video Graphics Array and 8514/A devices to optimize video subsystem performance. The video dot clock output may be one of 15 internally generated frequencies or one external input. The selection of the video dot clock frequency is done through four inputs. VSELO VSEL1
1.1
DESCRIPTION
VSEL2 VSEL3 VSELO and VSEL 1 are latched by the SELEN signal. VSEL2 and VSEL3 are used as direct inputs to the VCLK selection. Table 1-1 is the truth table for VCLK selection.
II
The Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C64) is capable of producing different output frequencies under firmware control. The video output frequency is derived from a 14.318 MHz system clock available in IBM PC/XT/AT and Personal System/2 computers. It is designed to work with Western Digital
Copyright © 1991 Integrated Circuit Systems, Inc. Reprinted with permission of Integrated Circuit Systems, Inc. Integrated Circuit Systems reserves the right to make any changes in the circuitry or specifications at any time without notice and assumes no responsibility for the use of any circuits described herein and makes no representation that they are free from patent infringement.
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ICS90C64
The input and truth table have been designed to allow a direct connection to one of the many Western Digital VGA controllers or 8514/A chip sets.
CLK1
INTRODUCTION
•
ICS90C64M
DVCC VCLK VCLKE N.C. AGND AVCC MLKE N.C. MLCK MSEL1
The MCLK output is one of eight internally generated frequencies as shown in Table 1-2. The various VCLK and MCLK frequencies are derived from the 14.318 MHz Input frequency. The VCLKE and MCLKE input can tristate the VCLK and MCLK outputs to facilitate board level testing.
MSEL2 EXTCLK VSEL1 VSELO SELEN VSEL2 VSEL3
1.2
FEATURES
Dual Clock generator for the IBM compatible Western Digital Video Graphics Array (VGA) LSI devices, and 8514/A chip sets. Integral loop filter components. Reduces cost and phase jitter. Generates 15 video clock frequencies (including 25.175 and 28.322 MHz) derived from a 14.318 MHz system clock reference frequency. On-chip generation of eight memory clock frequencies. Video clock is selectable among the 15 internally generated clocks and one external clock. CMOS technology.
MSELO DGND
20-PIN S.O.DIAGRAM
Backward compatibility to the WD90C63 and WD90C61 device. Available in a 20-pin PLCC, S.O., and DIP packages.
Ordering Information
ICS90C64V (PLCC Package) ICS90C64M (S.O. Package) ICS90C64N (DIP Package)
Note: ICS90C.