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8042AH Dataheets PDF



Part Number 8042AH
Manufacturers Intel
Logo Intel
Description Universal Peripheral Interface 8-Bit Slave Microcontroller
Datasheet 8042AH Datasheet8042AH Datasheet (PDF)

UPI-41AH 42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER Y Y UPI-41 6 MHz UPI-42 12 5 MHz Pin Software and Architecturally Compatible with all UPI-41 and UPI-42 Products 8-Bit CPU plus ROM OTP EPROM RAM I O Timer Counter and Clock in a Single Package 2048 x 8 ROM OTP 256 x 8 RAM on UPI-42 1024 x 8 ROM OTP 128 x 8 RAM on UPI-41 8-Bit Timer Counter 18 Programmable I O Pins One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface DMA Interrupt or Polled Ope.

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UPI-41AH 42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER Y Y UPI-41 6 MHz UPI-42 12 5 MHz Pin Software and Architecturally Compatible with all UPI-41 and UPI-42 Products 8-Bit CPU plus ROM OTP EPROM RAM I O Timer Counter and Clock in a Single Package 2048 x 8 ROM OTP 256 x 8 RAM on UPI-42 1024 x 8 ROM OTP 128 x 8 RAM on UPI-41 8-Bit Timer Counter 18 Programmable I O Pins One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface DMA Interrupt or Polled Operation Supported Y Fully Compatible with all Intel and Most Other Microprocessor Families Interchangeable ROM and OTP EPROM Versions Expandable I O Sync Mode Available Over 90 Instructions 70% Single Byte Available in EXPRESS Standard Temperature Range inteligent Programming Algorithm Fast OTP Programming Available in 40-Lead Plastic and 44Lead Plastic Leaded Chip Carrier Packages (See Packaging Spec Order Package Type P and N 240800-001) Y Y Y Y Y Y Y Y Y Y Y The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer to develop customized solutions for peripheral device control They are essentially ‘‘slave’’ microcontrollers or microcontrollers with a slave interface included on the chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM (OTP) All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to production level designs 210393 – 2 Figure 1 DIP Pin Configuration 210393 – 3 Figure 2 PLCC Pin Configuration November 1994 Order Number 210393-008 Free Datasheet http://www.datasheet4u.com/ UPI-41AH 42AH 210393 – 1 Figure 3 Block Diagram UPI PRODUCT MATRIX UPI Device 8042AH 8242AH 8742AH 8041AH 8741AH 1K 1K ROM 2K 2K 2K OTP EPROM RAM 256 256 256 128 128 12 5V 12 5V Programming Voltage THE INTEL 8242 As shown in the UPI-42 product matrix the UPI-42 will be offered as a pre-programmed 8042 with several software vendors’ keyboard controller firmware The current list of available 8242 versions include keyboard controller firmware from both Phoenix Technologies Ltd IBM and Award Software Inc The 8242 is programmed with Phoenix Technologies Ltd keyboard controller firmware for AT-compatible systems This keyboard controller is fully compatible with all AT-compatible operating systems and applications The 8242PC also contains Phoenix Technologies Ltd firmware This keyboard controller provides support for AT PS 2 and most EISA platforms as well as PS 2-style mouse support for either AT or PS 2 platforms The Intel 8242BB is programmed with IBM’s keyboard controller firmware The 8242BB provides an off the shelf keyboard and auxiliary device controller for AT PS 2 EISA and PCI architectures The 8242WA contains Award Software Inc firmware This device provides at AT-compatible keyboard controller for use in IBM PC AT compatible computers The 8242WB contains a version of Award Software Inc firmware that provides PS 2 style mouse support in addition to the standard features of the 8242WA Contact factory for current code revision available in all versions of the 8242 product lines 2 Free Datasheet http://www.datasheet4u.com/ UPI-41AH 42AH Table 1 Pin Description Symbol DIP Pin No 1 39 PLCC Pin Type No 2 43 I Name and Function TEST 0 TEST 1 TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) also functions as the event timer input (under software control) TEST 0 (T0) is used during PROM programming and ROM EPROM verification It is also used during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1 See the Sync Mode Section INPUTS Inputs for a crystal LC or an external timing signal to determine the internal oscillator frequency RESET Input used to reset status flip-flops and to set the program counter to zero RESET is also used during EPROM programming and verification SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM) This should be tied to a 5V when not used This pin is also used to put the device in Sync Mode by applying 12 5V to it CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EXTERNAL ACCESS External access input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WRITE I O wri.


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