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HYMP41GP72CNP4L-C4 Dataheets PDF



Part Number HYMP41GP72CNP4L-C4
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 240pin DDR2 VLP Registerd DIMMs based on 1Gb C version
Datasheet HYMP41GP72CNP4L-C4 DatasheetHYMP41GP72CNP4L-C4 Datasheet (PDF)

240pin DDR2 VLP Registerd DIMMs based on 1Gb C version This Hynix DDR2 VLP(Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb C version DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb C version based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. ORDERING INFORMATION Part Name HYMP112.

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Document
240pin DDR2 VLP Registerd DIMMs based on 1Gb C version This Hynix DDR2 VLP(Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb C version DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb C version based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. ORDERING INFORMATION Part Name HYMP112P72CP8L-C4/Y5/S6 HYMP125P72CP4L-C4/Y5/S6 HYMP351P72CMP4L-C4/Y5/S6 HYMP41GP72CNP4L-C4/Y5 Density 1GB 2GB 4GB 8GB Org. 128Mbx72 256Mbx72 512Mbx72 1Gbx72 Component Configuration 128Mbx8(HY5PS1G821CFP)*9 256Mbx4(HY5PS1G421CFP)*18 512Mbx4(HY5PS2G421CMP)*18 1Gbx4(HY5PS4G421CNP)*18 Ranks 1 1 2 4 Parity Support O O O O Note: 1. “P” of part number[12th digit] stands for Lead free products. SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 400 533 800 6-6-6 Unit Mbps Mbps Mbps Mbps tCK This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / May. 2008 1 Free Datasheet http://www.datasheet4u.com/ 1240pin DDR2 VLP Registered DIMMs FEATURES • • • • • • • • • • • • • • • • • • JEDEC standard 1.8V +/- 0.1V Power Supply VDDQ : 1.8V +/- 0.1V All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Average Auto Refresh Period 7.8us under TCASE 85 , 3.9us at 85 High Temperature Self-Refresh Entry enablble features PASR(Partial Array Self- Refresh) 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA 133.35 x 18.29 mm form factor Lead-free Products are RoHS compliant < TCASE 95 ADDRESS TABLE Density 1GB 2GB 4GB 8GB Organization Ranks 128Mb x 72 256Mb x 72 512Mb x 72 1Gb x 72 1 1 2 4 SDRAMs 128Mb x 8 256Mb x 4 256Mb x 4 256Mb x 4 # of DRAMs 9 18 36 72 # of row/bank/column Address 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m Rev. 0.2 / May. 2008 Free Datasheet http://www.datasheet4u.com/ 1240pin DDR2 VLP Registered DIMMs Input/Output Functional Description Symbol CK0 CK0 CKE[1:0] S[1:0] ODT[1:0] RAS, CAS, WE Vref VDDQ BA[1:0] Type IN IN IN IN IN IN Supply Supply IN Polarity Positive Edge Pin Description Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Negative Negative line of the differential pair of system clock inpu.


HYMP351P72CMP4L-S6 HYMP41GP72CNP4L-C4 HYMP41GP72CNP4L-Y5


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