v3.2
SX Family FPGAs
u e
™
Leading Edge Performance
320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew
Features
66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance Very Low...
