SLG505YC264C

SLG505YC264C Clock Synthesizer for Intel PCI-Express Gen2 Chipset Features SLG505YC264C is fully compliant to Intel CK505 clock specification revision 1.0 SRC clocks compliant to PCI-Express Gen2 reference clock requirement (except SRC_0 and SRC_1) TME (Trusted Mode Enable) input to disable over-clocking support Two programmable single-ended outputs - 25MHz for LAN PHY with Wake-on-LAN support and 24.576MHz for 1394A controller 3.3 and low voltage (0.8V) I/O Power Supply Available in both commercial and industrial temperature ranges 64 pin TSSOP Package Output Summary 2- differential CPU clock outputs @ 0.8V 1 - selectable differential CPU/SRC clock output @ 0.8V 1 - selectable differential DOT96/SRC clock output @ 0.8V 9 - differential Serial Reference Clock (SRC) clock outputs @ 0.8V 1 - selectable differential SATA/SRC clock output @ 0.8V 1 - single-ended 48MHz clock output @ 3.3V 6 - single-ended 33MHz clock outputs @ 3.3V 1 - single-ended 14.318MHz clock output @ 3.3V Pin Configuration Table 1. Frequency Select Table (FS_C, FS_B, FS_A) F S _ C 0 0 0 0 1 1 1 1 F S _ B 0 0 1 1 0 0 1 1 F S _ A 0 1 0 1 0 1 0 1 DOT_ 96 (MHz) 96.0 96.0 96.0 96.0 96.0 96.0 96.0 PCI_0/CLKREQ_A# VDD_PCI CPU (MHz) 266.6 133.3 200.0 166.6 333.3 100.0 400.0 SRC (MHz) 100.0 100.0 100.0 100.0 100.0 100.0 100.0 PCI (MHz) 33.3 33.3 33.3 33.3 33.3 33.3 33.3 REF (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB (MHz) 48.0 48.0 48.0 48.0 48.0 48.0 48.0 PCI_1/CLKREQ...