AK8441

[AK8441] AK8441 6 Channel 10 Bit 35MSPS/ch AFE for Linear CCD Device Outline The AK8441 is a +3.3 V CMOS, 6 Channels 10 Bit 10M~35MSPS/ch ADC which integrates on-chip Offset Adjust DAC, Gain Adjust PGA and CDS circuit. The device is optimized for Flatbed Scanner applications etc. Features … … … … … … … … … … … … … … Maximum conversion rate : Input range : Input polarity : 6ch. sampling : Offset DAC : 35MSPS / ch. 1.26Vpp(typ.)@CDS mode/ 1.2V(typ.)@Clamp mode Negative polarity only CDS circuit (Correlated Double Sampling) Separate 6 channel 8bit DAC with automatic black offset loop. PGA : Linearity : LVDS output : Timing Generator : 4 line serial register Gain range 0dB~18dB , 6bit, 6 channel DNL = −1LSB(min.), +1LSB(max.) Monotone guarantee 5LVDS-Data+LVDS-Clock Generate internal drive pulses(SHR,SHD,ADCK,OBP,CLPB) Write and read-back available , Single access mode / Continuous access mode Power supplies : AVDD:1.7~2.0V/AVDD3,PVDD,SVDD,LVDD:3.0~3.6V, IOVDD: 1.7~3.6V Operation Temperature: Power consumption : Package: 0°C~70°C 661mW (typ.)@6ch.mode, 35MSPS / channel 80 pin LQFP ,Pin Pitch 0.5mm, Mold Size 12mm×12mm MS0942-E-00 1 2011/08 Free Datasheet http://www.datasheet4u.com/ [AK8441] Circuit Block DAREF AVDD3 IOVDD SVDD IOVSS VCLP PVDD SVSS PVSS AVDD AVSS VST VCOM AVSS LVDD LVSS LVDS_Tx. LVDO0P LVDO0N LVDO1P LVDO1N Serializer & LVDS 10 10 PGA ADC 10bit 35MSPS AISET VRP VRN Reference Voltage CCDIN0 REFIN0 REFIN1 CCDIN1 Clamp CDS Clamp CDS DAC DAC PGA ADC 10bit 35...