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H5TC8G43AMR-xxA Dataheets PDF



Part Number H5TC8G43AMR-xxA
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 8Gb DDR3L SDRAM
Datasheet H5TC8G43AMR-xxA DatasheetH5TC8G43AMR-xxA Datasheet (PDF)

8Gb DDR3L SDRAM 8Gb DDR3L SDRAM (Dual Die Package) Lead-Free&Halogen-Free (RoHS Compliant) H5TC8G43AMR-xxA H5TC8G83AMR-xxA H5TC8G63AMR-xxA * SK hynix reserves the right to change products or specifications without notice. Rev. 0.4 / Apr. 2013 1 Free Datasheet http://www.datasheet4u.com/ Revision History Revision No. 0.1 0.2 0.3 0.4 History Initial Release Added Package Pin out and Addressing Typo collected : IDD Specification Editorial PKG Dimension Draft Date Nov. 2012 Jan. 2013 Mar. 2013 .

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8Gb DDR3L SDRAM 8Gb DDR3L SDRAM (Dual Die Package) Lead-Free&Halogen-Free (RoHS Compliant) H5TC8G43AMR-xxA H5TC8G83AMR-xxA H5TC8G63AMR-xxA * SK hynix reserves the right to change products or specifications without notice. Rev. 0.4 / Apr. 2013 1 Free Datasheet http://www.datasheet4u.com/ Revision History Revision No. 0.1 0.2 0.3 0.4 History Initial Release Added Package Pin out and Addressing Typo collected : IDD Specification Editorial PKG Dimension Draft Date Nov. 2012 Jan. 2013 Mar. 2013 Apr. 2013 Remark Rev. 0.4 / Apr. 2013 2 Free Datasheet http://www.datasheet4u.com/ Description The H5TC8G43AMR-xxA, H5TC8G83AMR-xxA and H5TC8G63AMR-xxA are a 8Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.) SK hynix 8Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC • On chip DLL align DQ, DQS and DQS transition with CK  • JEDEC standard 78ball FBGA(x4/x8), 96bal FBGA(x16) transition • Driver strength selected by EMRS • DM masks write data-in at the both rising and falling  • Dynamic On Die Termination supported edges of the data strobe • Asynchronous RESET pin supported • All addresses and control inputs except data,  • ZQ calibration supported data strobes and data masks latched on the  rising edges of the clock • TDQS (Termination Data Strobe) supported (x8 only) • Programmable CAS latency 6, 7, 8, 9, 10 and 11  supported • Programmable additive latency 0, CL-1, and CL-2  supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks  • Write Levelization supported • 8 bit pre-fetch • This product in compliance with the RoHS directive. Rev. 0.4 / Apr. 2013 3 Free Datasheet http://www.datasheet4u.com/ ORDERING INFORMATION Part No. H5TC8G43AMR-*xxA H5TC8G83AMR-*xxA H5TC8G63AMR-*xxA Configuration 2G x 4 1G x 8 512M x 16 Package 78ball FBGA 96ball FBGA * xx means Speed Bin Grade OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 -PB Frequency [MHz] CL5 667 667 667 CL6 800 800 800 CL7 1066 1066 1066 CL8 1066 1066 1066 1333 1333 1333 1333 1600 CL9 CL10 CL11 Remark (CL-tRCD-tRP) DDR3-1066 7-7-7 DDR3-1333 9-9-9 DDR3-1600 11-11-11 Rev. 0.4 / Apr. 2013 4 Free Datasheet http://www.datasheet4u.com/ Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 78ball FBGA Package 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ ODT1 ODT0 CS1 VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 NF VDDQ VSS VDD CS0 BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS NF RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NF DM DQ1 VDD NF CK CK A10/AP A15 A12/BC A1 A11 A14 7 8 VSS VSSQ DQ3 VSS NF VSS VDD ZQ0 VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ CKE1 CKE0 ZQ1 VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N Note: NF (No Function) - This is applied to balls only used in x4 configuration. 1 2 3 A B C D E F G H J K L M N 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.4 / Apr. 2013 5 Free Datasheet http://www.datasheet4u.com/ x8 Package Ball out (Top view): 78ball FBGA Package 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ ODT1 ODT0 CS1 VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS0 BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NF/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP A15 A12/BC A1 A11 A14 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ0 VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ CKE1 CKE0 ZQ1 VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 1 2 3 A B C D E F G H J K L M N 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.4 / Apr. 2013 6 Free Datasheet http://www.datasheet4u.com/ x16 Package Ball out (Top view): 96ball FBGA Package 1 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ ODT1 ODT0 CS1 VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS0 BA0 A3 A5 A7 RESET 2 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP NC A12/.


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