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ADP5050 Dataheets PDF



Part Number ADP5050
Manufacturers Analog Devices
Logo Analog Devices
Description 5-Channel Integrated Power Solution
Datasheet ADP5050 DatasheetADP5050 Datasheet (PDF)

5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator Data Sheet FEATURES Wide input voltage range: 4.5 V to 15 V ±1.5% output accuracy over full temperature range 250 kHz to 1.4 MHz adjustable switching frequency Adjustable/fixed output options via factory fuse or I2C interface I2C interface with interrupt on fault conditions Power regulation Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A sync buck regulators with low-side FET driver Channel 3 and Channel.

  ADP5050   ADP5050


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5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator Data Sheet FEATURES Wide input voltage range: 4.5 V to 15 V ±1.5% output accuracy over full temperature range 250 kHz to 1.4 MHz adjustable switching frequency Adjustable/fixed output options via factory fuse or I2C interface I2C interface with interrupt on fault conditions Power regulation Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A sync buck regulators with low-side FET driver Channel 3 and Channel 4: 1.2 A sync buck regulators Channel 5: 200 mA low dropout (LDO) regulator Single 8 A output (Channel 1 and Channel 2 operated in parallel) Dynamic voltage scaling (DVS) for Channel 1 and Channel 4 Precision enable with 0.8 V accurate threshold Active output discharge switch Programmable phase shift in 90° steps Individual channel FPWM/PSM mode selection Frequency synchronization input or output Optional latch-off protection on OVP/OCP failure Power-good flag on selected channels Low input voltage detection Overheat detection on junction temperature UVLO, OCP, and TSD protection 48-lead, 7 mm × 7 mm LFCSP package −40°C to +125°C junction temperature C1 C0 FB1 PVIN1 ADP5050 TYPICAL APPLICATION CIRCUIT ADP5050 VREG VDD SYNC/MODE INT VREG OSCILLATOR 100mA RT 4.5V TO 15V C2 COMP1 EN1 SS12 CHANNEL 1 BUCK REGULATOR (1.2A/2.5A/4A) BST1 SW1 VREG DL1 PGND DL2 RILIM1 RILIM2 Q2 CHANNEL 2 BUCK REGULATOR (1.2A/2.5A/4A) VREG SW2 BST2 EN2 FB2 C6 L2 VOUT2 C7 Q1 C3 L1 VOUT1 C4 C5 PVIN2 COMP2 PVIN3 C8 COMP3 EN3 SS34 CHANNEL 3 BUCK REGULATOR (1.2A) BST3 SW3 FB3 PGND3 BST4 C9 L3 VOUT3 C10 PVIN4 C11 COMP4 EN4 CHANNEL 4 BUCK REGULATOR (1.2A) SW4 FB4 PGND4 CHANNEL 5 200mA LDO REGULATOR VOUT5 FB5 C12 L4 VOUT4 C13 1.7V TO 5.5V http://www.DataSheet4U.com/ PVIN5 EN5 VOUT5 C15 C14 VDDIO SCL SDA I2C ALERT PWRGD nINT 10899-001 APPLICATIONS Small cell base stations FPGA and processor applications Security and surveillance Medical applications EXPOSED PAD Figure 1. GENERAL DESCRIPTION The ADP5050 combines four high performance buck regulators and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15 V with no preregulators. Channel 1 and Channel 2 integrate high-side power MOSFETs and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration can provide a single output with up to 8 A of current. Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver output current of 1.2 A. Rev. 0 Document Feedback One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com The switching frequency of the ADP5050 can be programmed or synchronized to an external clock. The ADP5050 contains a precision enable pin on each channel for easy power-up sequencing or adjustable UVLO threshold. The ADP5050 integrates a general-purpose LDO regulator with low quiescent current and low dropout voltage that provides up to 200 mA of output current. The optional I2C interface provides the user with flexible configuration options, including adjustable and fixed output voltage options, junction temperature overheat warning, low input voltage detection, and dynamic voltage scaling (DVS). Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. ADP5050 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Detailed Functional Block Diagram .............................................. 4 Specifications..................................................................................... 5 Buck Regulator Specifications .................................................... 6 LDO Regulator Specifications .................................................... 8 I2C Interface Timing Specifications ........................................


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