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BU-61586 Dataheets PDF



Part Number BU-61586
Manufacturers DDC
Logo DDC
Description Bus Controller / Remote Terminal / Monitor Terminal - BC/RT/MT
Datasheet BU-61586 DatasheetBU-61586 Datasheet (PDF)

BU-65170/61580 and BU-61585 MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE) ACE User’s Guide Also Available DESCRIPTION DDC's BU-65170, BU-61580 and BU-61585 Bus Controller / Remote Terminal / Monitor Terminal (BC/RT/MT) A d v a n c e d Communication Engine (ACE) terminals comprise a complete integrated interface between a host processor and a MIL-STD-1553 A and B or STANAG 3838 bus. The ACE series is packaged in a 1.9 square-inch, 70-pin, low-profile, cofired Multi.

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BU-65170/61580 and BU-61585 MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE) ACE User’s Guide Also Available DESCRIPTION DDC's BU-65170, BU-61580 and BU-61585 Bus Controller / Remote Terminal / Monitor Terminal (BC/RT/MT) A d v a n c e d Communication Engine (ACE) terminals comprise a complete integrated interface between a host processor and a MIL-STD-1553 A and B or STANAG 3838 bus. The ACE series is packaged in a 1.9 square-inch, 70-pin, low-profile, cofired MultiChip Module (MCM) ceramic package that is well suited for applications with stringent height requirements. The BU-61585 ACE integrates dual transceiver, protocol, memory management, processor interface logic, and a total of 12K words of RAM in a choice of DIP or flat pack packages. The BU-61585 requires +5 V power and either -15 V or -12 V power. The BU-61585 internal RAM can be configured as 12K x 16 or 8K x 17. The 8K x 17 RAM feature provides capability for memory integrity checking by implementing RAM parity generation and verification on all accesses. To minimize board space and “glue” logic, the ACE provides ultimate flexibility in interfacing to a host processor and internal/external RAM. The advanced functional architecture of the ACE terminals provides software compatibility to DDC's Advanced Integrated Multiplexer (AIM) series hybrids, while incorporating a multiplicity of architectural enhancements. It allows flexible operation while off-loading the host processor, ensuring data sample consistency, and supports bulk data transfers. The ACE hybrids may be operated at either 12 or 16 MHz. Wire bond options allow for programmable RT address (hardwired is standard) and external transmitter inhibit inputs. http://www.DataSheet4U.net/ FEATURES • Fully Integrated MIL-STD-1553 Interface Terminal Interface • Flexible Processor/Memory • Standard 4K x 16 RAM and • Optional RAM Parity Optional 12K x 16 or 8K x 17 RAM Available Generation/Checking • Automatic BC Retries • Programmable BC Gap Times • BC Frame Auto-Repeat • Flexible RT Data Buffering • Programmable Illegalization • Selective Message Monitor • Simultaneous RT/Monitor Mode TX/RX_A SHARED RAM CH. A TRANSCEIVER A DATA BUFFERS PROCESSOR DATA BUS * TX/RX_A DATA BUS DUAL ENCODER/DECODER, MULTIPROTOCOL AND MEMORY MANAGEMENT D15-D0 TX/RX_B ADDRESS BUS ADDRESS BUFFERS A15-A0 PROCESSOR ADDRESS BUS CH. B TRANSCEIVER B TX/RX_B PROCESSOR AND MEMORY INTERFACE LOGIC TRANSPARENT/BUFFERED, STRBD, SELECT, RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN, MSB/LSB/DTGRT IOEN, MEMENA-OUT, READYD ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR, 8/16-BIT/DTREQ, POLARITY_SEL/DTACK INT PROCESSOR AND MEMORY CONTROL INTERRUPT REQUEST RT ADDRESS RTAD4-RTAD0, RTADP INCMD MISCELLANEOUS CLK_IN, TAG_CLK, MSTCLR,SSFLAG/EXT_TRG * SEE ORDERING INFORMATION FOR AVAILABLE MEMORY FIGURE 1. ACE BLOCK DIAGRAM © 1992, 1999 Data Device Corporation datasheet pdf - http://www.DataSheet4U.net/ TABLE 1. “ACE” SERIES SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage ! Logic +5V ! Transceiver +5V ! -15V ! -12V Logic ! Voltage Input Range RECEIVER Differential Input Resistance ! (BU-65170/61580/61585X1, BU-65170/61580/61585X2) (Notes 1-7) ! (BU-65170/61580/61585X3, BU-65170/61580/61585X6) (Notes 1-7) Differential Input Capacitance ! (BU-65170/61580/61585X1, BU-65170/61580/61585X2) (Notes 1-7) ! (BU-65170/61580/61585X3, BU-65170/61580/61585X6) (Notes 1-7) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage ! Direct Coupled Across 35 Ω, Measured on Bus ! Transformer Coupled Across 70 Ω, Measured on Bus •(BU-65170/61580/61585X1) •(BU-65170/61580/61585X2,X3, X6) Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time LOGIC VIH VIL IIH (Vcc=5.5V, VIN=Vcc) IIH (Vcc=5.5V, VIN=2.7V) ! SSFLAG/EXT_TRIG ! All Other Inputs IIL (Vcc=5.5V, VIN=0.4V) ! SSFLAG/EXT_TRIG ! All Other Inputs VOH (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOH=max) VOL (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOL=max) IOL ! DB15-DB0, A15-A0, MEMOE/ ADDR_LAT, MEMWR/ ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL MIN TYP MAX UNITS TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD) PARAMETER LOGIC (cont’d) ! INCMD, INT MEMENA_OUT, READYD, IOEN, TXA, TXA, TXB, TXB, TX_INH_OUT_A, TX_INH_OUT_B, IOH ! DB15-DB0, A15-A0, MEMOE/ ADDR_LAT, MEMWR/ ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL ! INCMD, INT, MEMENA_OUT, READYD, IOEN, TXA, TXA, TXB, TXB, TX_INH_OUT_A, TX_INH_OUT_B, CI (Input Capacitance) CIO (Bi-directional signal input capacitance) POWER SUPPLY REQUIREMENTS Voltages/Tolerances ! BU-65170/61580/61585X1 • +5V (Logic) • +5V (Ch. A, Ch. B) • -15V (Ch. A, Ch. B) ! BU-65170/61580/61585X2 • +5V (Logic) • +5V (Ch. A, Ch. B) • -12V (Ch. A, Ch. B) ! BU-65170/61580/61585X3, BU-65170/61580/61585X6 • +5V (Logic) • +5V (Ch. A, Ch. B) Current Drain (Total Hybrid) ! BU-65170/61580X1 • +5V (Logic, Ch. A, Ch. B) • -15V (Ch. A, Ch. B) • Idle • 25% Tra.


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