Document
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller
Rev. 1 — 4 June 2012 Product data sheet
1. General description
The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.
2. Features and benefits
2.1 Key features
CPU platform 270 MHz, 32-bit ARM926EJ-S 16 kB D-cache and 16 kB I-cache Memory Management Unit (MMU) Internal memory 192 kB embedded SRAM External memory interface NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only) 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM Security AES decryption engine (LPC3143 only) Secure one-time programmable memory for AES key storage and customer use 128 bit unique ID per device for DRM schemes Communication and connectivity High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY Two I2S interfaces Integrated master/slave SPI Two master/slave I2C-bus interfaces Fast UART Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA Four-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface System functions Dynamic clock gating and scaling Multiple power domains
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Datasheet pdf - http://www.DataSheet4U.co.kr/
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB On the LPC3143 only: secure booting using an AES decryption engine from SPI flash, NAND flash, SD/MMC cards, UART, or USB. DMA controller Four 32-bit timers Watchdog timer PWM module Master/slave PCM interface Random Number Generator (RNG) General Purpose I/O pins (GPIO) Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access Operating voltage and temperature Core voltage: 1.2 V I/O voltages: 1.8 V, 3.3 V Temperature: 40 C to +85 C TFBGA180 package: 12 x 12 mm, 0.8 mm pitch
3. Ordering information
Table 1. Ordering information Package
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Type number
Name
Description
Version
LPC3141FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12 12 0.8 mm SOT570-3 LPC3143FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12 12 0.8 mm SOT570-3
3.1 Ordering options
Table 2. Ordering options for LPC3141/3143 Core/bus Total frequency SRAM Security High-speed USB engine AES no yes Device/ Host/OTG Device/ Host/OTG 10-bit I2S/ ADC I2C channels 4 4 MCI Temperature SDHC/ range SDIO/ CE-ATA 40 C to +85 C 40 C to +85 C Type number
LPC3141FET180 LPC3143FET180
270/ 90 MHz 270/ 90 MHz
192 kB 192 kB
2 each yes 2 each yes
LPC3141_43
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2012
2 of 69
Datasheet pdf - http://www.DataSheet4U.co.kr/
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
4. Block diagram
JTAG interface
LPC3141/3143
DATA CACHE 16 kB
TEST/DEBUG INTERFACE INSTRUCTION CACHE 16 kB
ARM926EJ-S
DMA CONTROLLER
USB 2.0 HIGH-SPEED OTG master slave slave ROM slave 96 kB ISRAM0 slave 96 kB ISRAM1 slave NAND CONTROLLER AES(1) BUFFER
master slave INTERRUPT CONTROLLER slave MPMC master master
slave
MULTI-LAYER AHB MATRIX
slave MCI SD/SDIO slave AHB TO APB BRIDGE 0/ ASYNC slave AHB TO APB BRIDGE 1/ ASYNC slave AHB TO APB BRIDGE 2/ ASYNC slave AHB TO APB BRIDGE 3/ ASYNC
slave AHB TO APB BRIDGE 4/ SYNC
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APB slave group 0 WDT SYSTEM CONTROL CGU IOCONFIG
APB slave group 4 NAND REGISTERS DMA REGISTERS
APB slave group 3 I2S0 I2S1
10-bit ADC EVENT ROUTER RNG OTP APB slave group 1 TIMER 0/1/2/3 PWM I2C0
(1)LPC3143 only
APB slave group 2 UART LCD SPI PCM
I2C1
002aae081
Fig 1.
LPC3141/3143 block diagram
LPC3141_43
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2012
3 of 69
Datasheet pdf - http://www.DataSheet4U.co.kr/
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
5. Pinning information
5.1 Pinning
ball A1 index area
LPC3141/3143
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A B C D E F G H J K L M N P
002aae082
Transparent top view
Fig 2. Table 3. Row A 1 5 9 13 1 5 9 13 1 5 9 13 1 5 9 13
LPC3141/3143 pinning TFBGA180 package Pin allocation table
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Pin Symbol EBI_D_10 mGPIO7 VPP ADC10B_VDDA33 EBI_D_8 mGPIO8 PWM_DATA ADC10B_GPA2 EBI_D_7 mGPIO9 VPP VDDE.