Document
VNI8200XP / VNI8200XP-32
Datasheet
Octal high-side smart power solid-state relay with serial/parallel selectable interface on-chip
PowerSSO-36 package with exposed pad down (EPD)
Product status link VNI8200XP
VNI8200XP-32 Product label
Features
• Voltage operating range 10.5 V to 36 V • UVLO with hysteresis • Output current: 0.7 A or 1.0 A (VNI8200XP or VNI8200XP-32) per channel • Low supply current in OFF (1 mA) and ON (5.3 mA) state • 5 V and 3.3 V compatible I/Os • Selectable interface on logic side SPI or parallel • 5 MHz SPI (8 or 16-bits) with output enable, daisy chain and MCU freeze
detection • 100 mA DC-DC with integrated boot diode and adjustable output voltage • 4x2 LED matrix for efficient outputs state LEDs driving • Can drive all type (resistive, capacitive, inductive) of loads • Per-channel overload and short-circuit protection • Per-channel/independent overtemperature protection • Fast demagnetization of inductive loads (Vout clamp) • Overvoltage protection (VCC clamping) • Loss of GND protection • Power Good (supply voltage level) diagnostic • Common fault open drain output • IC warning temperature detection • PowerSSO-36 (10.3 x 10.3 mm) package • Designed to meet IEC61131-2, IEC61000-4-2, IEC61000-4-4 and
IEC61000-4-5
Application
• Programmable logic control • Industrial PC peripheral input/output • Numerical control machines
Description
The VNI8200XP and VNI8200XP-32 are monolithic 8-channel drivers, designed in STMicroelectronics™ VIPower™ technology, intended to drive any kind of load with one side connected to ground. Both ICs operates from 10.5 V to 36 V and feature a very low supply current, parallel or 4-wires SPI control interface, 4x2 LED matrix and a micropower step-down switching regulator with peak current control loop mode.
DS11044 - Rev 5 - May 2023 For further information contact your local STMicroelectronics sales office.
www.st.com
VNI8200XP / VNI8200XP-32
The SPI interface (enabled by SEL2 pin = H) can work up to 5 MHz in 8-bits (SEL1 = L), or 16-bits (SEL1 = H) with parity check and extended diagnostic (DC-DC operation, Case over-temperature, SPI Communication Fail, Power Good) information. In SPI mode the daisy chain is allowed, both the OUT_EN signal and the MCU freeze detection by whatchdog are available. If enabled (WD_EN voltage above 25% of VREG), the watchdog circuitry generates an internal reset on expiry of the internal watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse on the WD pin. The whatchdog timer can be programmed by the set voltage on WD_EN pin.
The internal LED matrix driver circuitry (4 rows, 2 columns) allows the efficient driving of the 8 LEDs reporting the on/off status of each of the 8 outputs. The VREG pin supplies both the logic output buffers and LED matrix. The 100 mA output current capability of the integrated step-down (featuring overload and short-circuit conditions) can be used to supply both the VREG pin and other application components (for example digital isolators or optocouplers).
Active per-channel current limitation (0.7 A and 1.0A for VNI8200XP and VNI8200XP-32, respectively), combined with channel-independent thermal shutdown, protect the circuitry against overload and short circuit. Built-in thermal shutdown protects each channel from over-temperature and overload: each overheated channel automatically turns OFF after its junction temperature triggers the protection threshold (TTSD). The channel turns back ON if its junction temperature decreases lower than restart threshold (TR). An additional case temperature sensor protects the whole chip against over-temperature: if the case temperature triggers the TCSD threshold then overloaded channels are turned OFF and restart only when case temperature decreased down to the reset threshold (TCR). Non overloaded channels continue to operate normally.
Loss of GND protection guarantees automatic turn off the outputs in case of ground wire break.
Dedicated diagnostic pins report the detection of: invalid voltage range on VCC rail (PG pin), case overtemperature (TWARN pin), SPI fault or junction over-temperature (FAULT pin).
DS11044 - Rev 5
page 2/37
VNI8200XP / VNI8200XP-32
Block diagram
1
Block diagram
Figure 1. Block diagram
PHASE BOOT DCVDD VREF
VCC
FB
VREG
PGOOD SEL1/IN1 WD_EN/IN2 OUT_EN/IN3
WD/IN4 SDI/IN5 CLK/IN6
SS/IN7 SDO/IN8
SEL2
FAULT TWARN
ROW0 ROW1
ROW2
ROW3
DC-DC CONTROL
LOGIC
SPI
VCC CLAMP
POWER GOOD
UNDERVOLTAGE LOCKOUT
x8 OUTPUT CLAMP
LED MATRIX
CURRENT LIMITATION
JUNCTION TEMP DETECTION
CASE TEMP DETECTION
OUTX
COL0
COL1
GND
DS11044 - Rev 5
page 3/37
2
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin connection
VNI8200XP / VNI8200XP-32
Pin connection
Figure 2. Pin connection (top view)
1 SEL2
2 SEL1/IN 1
3 WD_EN/IN 2
4 OUT_EN/IN 3 5 WD/IN 4 6 SDI/IN 5 7
CLK/IN 6 8
SS/IN 7 9 SDO/IN 8
10 VREG 11 COL0 12 COL1 13 DC VDD 14
VREF 15 ROW0 16 ROW1 17 ROW2 18 ROW3
TAB=Vcc
36 N.