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TC74HC112AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC112AP,TC74HC112AF,TC74HC112AFN
Dual J-K Flip Flop with Preset and Clear
The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse. CLR and PR are independent of the clock and are actived by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Note: xxxFN (JEDEC SOP) is not available in Japan. TC74HC112AP
TC74HC112AF
Features
• • • • • • • • High speed: fmax = 67 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 2 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ∼ tpHL Balanced propagation delays: tpLH − Wide operating voltage range: VCC (opr) = 2 to 6 V Pin and function compatible with 74LS112
TC74HC112AFN
Pin Assignment
Weight DIP16-P-300-2.54A SOP16-P-300-1.27A SOL16-P-150-1.27
: 1.00 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.)
1
2007-10-01
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TC74HC112AP/AF/AFN
IEC Logic Symbol
Truth Table
Inputs
CLR
Outputs K
PR
J
CK X X X
Q L H H Qn L H
Qn
Q
Function Clear Preset
L H L H H H H H
H L L H H H H H
X X X L L H H X
X X X L H L H X
H L H
Qn
No Change
H L Qn
Qn
Toggle No Change
Qn
X: Don’t care
System Diagram
2
2007-10-01
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TC74HC112AP/AF/AFN
Absolute Maximum Ratings (Note 1)
Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating
−0.5 to 7 −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 ±20 ±20 ±25 ±50
Unit V V V mA mA mA mA mW °C
500 (DIP) (Note 2)/180 (SOP)
−65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW.
Operating Ranges (Note)
Characteristics Supply voltage Input voltage Output voltage Operating temperature Symbol VCC VIN VOUT Topr Rating 2 to 6 0 to VCC 0 to VCC
−40 to 85
Unit V V V °C
0 to 1000 (VCC = 2.0 V) Input rise and fall time tr, tf 0 to 500 (VCC = 4.5 V) 0 to 400 (VCC = 6.0 V) ns
Note:
The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND.
3
2007-10-01
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TC74HC112AP/AF/AFN
Electrical Characteristics
DC Characteristics
Characteristics Symbol Test Condition VCC (V) 2.0 High-level input voltage VIH
⎯
Ta = 25°C Min 1.50 3.15 4.20
⎯ ⎯ ⎯
Ta = −40 to 85°C Max
⎯ ⎯ ⎯
Typ.
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Min 1.50 3.15 4.20
⎯ ⎯ ⎯
Max
⎯ ⎯ ⎯
Unit
4.5 6.0 2.0
V
0.50 1.35 1.80
⎯ ⎯ ⎯ ⎯ ⎯
0.50 1.35 1.80
⎯ ⎯ ⎯ ⎯ ⎯
Low-level input voltage
VIL
⎯
4.5 6.0 2.0
V
1.9 4.4 5.9 4.18 5.68
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18
⎯ ⎯
1.9 4.4 5.9 4.13 5.63
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
IOH = −20 μA High-level output voltage VOH VIN = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 μA Low-level output voltage VOL VIN = VIH or VIL IOL = 4 mA IOL = 5.2 mA Input leakage current Quiescent supply current IIN ICC VIN = VCC or GND VIN = VCC or GND
4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
V
0.1 0.1 0.1 0.26 0.26
±0.1
0.1 0.1 0.1 0.33 0.33
±1.0 μA μA
V
2.0
20.0
4
2007-10-01
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TC74HC112AP/AF/AFN
Timing Requirements (input: tr = tf = 6 ns)
Characteristics Symbol Test Condition VCC (V) Minimum pulse width ( CK ) tW (L) tW (H) 2.0
⎯
Ta = 25°C Typ.
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Ta = −40 to 85°C Limit 95 19 16
95 19 16 95 19 16 0 0 0 60 12 11 4 24 28
Unit
Limit 75 15 13
75 15 13 75 15 13 0 0 0 50 10 9 6 30 34
4.5 6.0
2.0
ns
Minimum pulse width.