LPC18xx ARM Cortex-M3 microcontroller
UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 2.8 — 10 December 2015
User manual
Document information
Info Conte...
Description
UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 2.8 — 10 December 2015
User manual
Document information
Info Content
Keywords
LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x, LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20, LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3, SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual
Abstract
LPC18xx user manual
NXP Semiconductors
UM10430
LPC18xx User manual
Revision history Rev Date
Description
2.8 Modifications:
20151210
LPC18xx user manual
Fixed formatting issues. Added CREG1 register. See Table 90 “CREG1 register (CREG1, address 0x4004 3008) bit
description”.
Updated text in Section 12.2.1 “Configuring the BASE_M3_CLK for high operating frequencies”: To
ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock BASE_M4_CLK as described in Section 12.2.1.1.
Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in Table 75 “Event router
inputs”; USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use for wake-up from sleep and deep-sleep mode; USB1: USB1 AHB_NEED_CLK signal. Not active in power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode.
Updated Table 170 “LPC1850/30/20/10 Pin description (flashless parts)”: Fixed PD_3 to be "SCT
Output 6"; was SCT Output 7.
UM10430
User manual
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