Document
INDEX
PRELIMINARY
MX23L6430
64M-Bit Synchronous Mask ROM
FEATURES
• Switchable organization : 4M x 16 ( word mode ) or 2M x 32 ( double word mode )
• Power supply 3.0V ~ 3.6V • TTL compatible with multiplexed address • All inputs are sampled at rising edge of system clock • Read performance :
- 4-1-1-1@33MHz(RAS Latency=1, CAS Latency=3 ) - 5-1-1-1@50MHz(RAS Latency=1, CAS Latency=4 ) - 7-1-1-1@66MHz(RAS Latency=2, CAS Latency=5 )
- 7-1-1-1@100MHz(RAS Latency=2, CAS Latency=5) - Clock to valid output delay (tSAC) : 6ns(Max.) • MRS cycle with address key programs : - RAS Latency : 1 & 2 - CAS Latency : 2 ~ 8 - Burst Length : 8 double word - Burst Type : Sequential or Interleaved • DQM for data-out masking • Package : 86 pin TSOP(II)
GENERAL DESCRIPTION
The 64M synch. MROM is a synchronous high bandwidth mask programmable ROM with MXIC's high performance CMOS process technology and is organized either as 4M x 16 bits or 2M x 32 bits depending on polarity of WORD pin. Synchronous design allows precise cycle control , with the use of system clock, I/O
transaction are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system application.
PIN CONFIGURATION
VCC
1
Q0
2
VCCQ
3
Q16
4
Q1
5
VSSQ
6
Q17
7
Q2
8
VCCQ
9
Q18
10
Q3
11
VSSQ
12
Q19
13
MR
14
VCC
15
DQM
16
NC
17
CAS
18
RAS
19
CS
20
WORD
21
A12
22
A11
23
A10
24
A0
25
A1
26
A2
27
NC
28
VCC
29
NC
30
Q4
31
VSSQ
32
Q20
33
Q5
34
VCCQ
35
Q21
36
Q6
37
VSSQ
38
Q22
39
Q7
40
VCCQ
41
Q23
42
VCC
43
MX23L6430
86
VSS
85
Q31
84
VSSQ
83
Q15
82
Q30
81
VCCQ
80
Q14
79
Q29
78
VSSQ
77
Q13
76
Q28
75
VCCQ
74
Q12
73
NC
72
VSS
71
NC
70
NC
69
NC
68
CLK
67
CKE
66
A9
65
A8
64
A7
63
A6
62
A5
61
A4
60
A3
59
NC
58
VSS
57
NC
56
Q27
55
VCCQ
54
Q11
53
Q26
52
VSSQ
51
Q10
50
Q25
49
VCCQ
48
Q9
47
Q24
46
VSSQ
45
Q8
44
VSS
P/N:PM0575
REV. 1.1, FEB. 09, 1999 1
INDEX
MX23L6430
BLOCK DIAGRAM
Row Decoder
ADD
Row Buffer Address Register
RA12-0
64M bits cell array
LRAS CKEB
Col. Buffer
CA7-3 CA2-0
Column Decoder CF2.0
Mode Register
LCAS
MRE
Timing Register
Output Bufer Sense AMP.
Q0 : :
Q31
LOE
CLK CKE
MR RAS
CAS
CS
DQM WORD
PIN DESCRIPTION
Symbol CLK CS CKE A0 ~ A12
RAS CAS MR Q0 ~ Q31 VDD/VSS VDDQ/VSSQ WORD
DQM NC
Name
Function
System Clock
Active on the rising edge to sample all inputs
Chip Select
Disable or enable device operation by masking or enabling all in-
puts except CLK and CKE
Clock Enable
Mask system clock to freeze operation from next clock cycle and
disable input buffers for power down in standby.
Address
Row/Column addresses are multiplexed on the same pins.
Row address : RA0~RA12 , Col. address : CA0~CA7(x32) or
CA0~CA8(x16)
Row address Strobe
Latch row addres.