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Data Sheet
PRELIMINARY April 2008
AR6002 ROCmTM Single-Chip MAC/BB/Radio for 2.4/5 GHz Embedded WLAN Applications
General Description
The Atheros AR6002 is the 2nd generation of the WLAN ROCm family. Building on the advanced performance and features of the AR6001 family, the compact size and low power consumption of this single chip design make it an ideal vehicle for adding WLAN to hand-held and other battery-powered consumer electronic devices. Both IEEE 802.11g (2.4 GHz) and 802.11a (5 GHz) standards are supported by the AR6002 family. The AR6002 supports both SDIO 1.1 and GSPI host interfaces. The AR6002 family includes a highly integrated, front-end module ((Power Amplifier, Low-Noise Amplifier and RF switch), enabling low-cost designs with minimal external components. The RF performance, data throughput, and power consumption further improve upon the performance of the AR6001 family. Advanced architecture and protocol techniques save power during sleep, stand-by and active states. Fast antenna diversity is also supported, allowing optimal antenna selection on a perpacket basis. The AR6002 family supports 2, 3 and 4 wire Bluetooth coexistence protocols with advanced algorithms for predicting channel usage by the co-located Bluetooth transceiver. are available in Wafer Level Chip Scale Packages (WLCSP) or Ball Grid Arrays (BGA) packaging .
AR6002 Features
■ All-CMOS IEEE 802.11a/b/g or 802.11b/g
single-chip client
■ Integrated PA, LNA and RF switch
minimizing external component count
■ Data rates of 1–54 Mbps for 802.11g, 6-54
Mbps for 802.11a
■ Advanced power management to minimize
standby, sleep and active power
■ Host interface support for SDIO and GSPI ■ Security support for WPS, WPA2, WPA,
The AR6002 family provides multiple peripheral interfaces including UART, SPI, I2C and 18 GPIO pins. All internal clocks are generated from a single external crystal/oscillator. A variety of reference clocks are supported which include 19.2, 24, 26, 38.4, 40 and 52 MHz. AR6002 chips
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WAPI and protected management frames ■ Support for 2.4 and 5 GHz operation in all available bands in all regulatory domains
■ Full 802.11e QoS support including WMM
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and U-APSD coexistence handshake support
■ Standard 2, 3 and 4 wire Bluetooth ■ IEEE 1149.1, JTAG, test access port and
boundary scan
■ 18 fully-programmable GPIO pins ■ 16550-compliant UART ■ SPI or I2C for EEPROM support ■ Internally generated low-frequency oscillator
for low-power sleep
■ Available in 7 x 7 mm BGA package with 0.5
mm pitch or WLCSP package with 0.4 mm pitch
SDIO
HOST SDIO or GSPI
GSPI
Mailbox DMA
A H B I N T E R N A L B U S
802.11a/g MAC
802.11a/g BB
802.11a/g Radio
PA
LNA1
LNA2
LNA2 Input
Console
UART SPI/I2C GPIO JTAG Bridge
Memory Controller
RAM ROM
i-port d-port
EEPROM
Xtensa CPU
LED
Test, ICE
AR6002
Power, Clock Management
LF CLK REF CLK
32 KHz OSC (optional) OSC/XTAL
AR6002 System Block Diagram
© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros™, ROCm™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
PRELIMINARY: ATHEROS CONFIDENTIAL
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www.DataSheet.co.kr
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AR6002 MAC/BB/Radio for Embedded WLAN Applications April 2008
Atheros Communications, Inc. PRELIMINARY: ATHEROS CONFIDENTIAL
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
Table of Contents
1 Functional Description ................. 5
1.1 Overview ................................................... 5 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 XTENSA CPU ....................................... 5 Virtual Memory Controller (VMC) .... 5 AHB and APB Blocks ........................... 5 Master SI/SPI Control ......................... 5 GPIO ....................................................... 6 LEDs ....................................................... 6 MBOX ..................................................... 6 UART ..................................................... 6 3.3 3.4 3.2 Transmitter (Tx) Block ....................... 22 3.2.1 Synthesizer (SYNTH) Block ... 22 Bias/Control (BIAS) Block ................ 23 Baseband Block ................................... 23 3.4.1 SM Block ................................... 24 3.4.2 AGC Block ................................... 24 3.4.3 TIM Block .................................... 24 3.4.4 FFT and VIT Blocks .................... 24 3.4.5 BBB Block ..................................... 25
4 Electrical Characteristics ............27
4.1 Absolute Maximum Ratings ................ 27 4.2 4.3 4.4 4.5 4.6 .