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A7367 Dataheets PDF



Part Number A7367
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description SAA7367
Datasheet A7367 DatasheetA7367 Datasheet (PDF)

www.DataSheet.co.kr INTEGRATED CIRCUITS DATA SHEET SAA7367 Bitstream conversion ADC for digital audio systems Product specification Supersedes data of 1996 Jun 17 File under Integrated Circuits, IC01 1998 Nov 17 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems FEATURES • Total Harmonic Distortion plus Noise (THD + N) = −88 dB (0.004%); DR = 93 dB; S/N = 97 dB • Simple interfacing .

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www.DataSheet.co.kr INTEGRATED CIRCUITS DATA SHEET SAA7367 Bitstream conversion ADC for digital audio systems Product specification Supersedes data of 1996 Jun 17 File under Integrated Circuits, IC01 1998 Nov 17 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems FEATURES • Total Harmonic Distortion plus Noise (THD + N) = −88 dB (0.004%); DR = 93 dB; S/N = 97 dB • Simple interfacing to analog inputs • Small, non-critical PCB layout • Low pin-out SO24 package (pin-compatible to SAA7366) • 4 flexible serial interface modes • 4.5 to 5.5 V operation • Standby mode • Detection of digital signal ≥−1 dB amplitude • Up to 18 significant bits serial output • Selectable high-pass filter. APPLICATIONS The device is designed for the digital acquisition of analog audio signals for digital audio systems such as: • Compact Disc-Recordable (CD-R) • Audio digital signal processing systems for hi-fi and musical instrument applications • Digital Audio Tape (DAT). QUICK REFERENCE DATA SYMBOL VDDD IDDD VDDA IDDA fBCK fs THD + N DR S/N PARAMETER digital supply voltage digital supply current analog supply voltage analog supply current clock input frequency sample rate total harmonic distortion plus noise dynamic range signal-to-noise ratio at 0 dB input at −60 dB CONDITIONS − 4.5 − 4.60 18 − 90 − MIN. 4.5 17 5.0 13 12.288 48 −88 93 97 TYP. 5.0 − 5.5 − 12.8 50 −80 − − GENERAL DESCRIPTION SAA7367 The SAA7367 is a CMOS low-cost stereo Analog-to-Digital Converter (ADC) using the Philips bitstream conversion technique. MAX. 5.5 V UNIT mA V mA MHz kHz dB dB dB ORDERING INFORMATION TYPE NUMBER SAA7367 PACKAGE NAME SO24 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT137-1 1998 Nov 17 2 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems BLOCK DIAGRAM SAA7367 handbook, full pagewidth VSSA 13 operational amplifier 16 17 operational amplifier VrefR 15 TESTB 12 STDB 2 BIR BOR REFERENCE VOLTAGE GENERATOR CLOCK GENERATION AND CONTROL 4 CKIN VDACP 19 SIGMADELTA MODULATOR TIMING GENERATOR SIGMADELTA MODULATOR DECIMATION FILTER STAGE 2 STAGE 1 3 HALF-BAND COMB FILTERS FILTER 5 6 VDDD VSSD Iref 14 REFERENCE CURRENT GENERATOR VDACN 18 SAA7367 HIGH-PASS FILTER 20 21 REFERENCE VOLTAGE GENERATOR operational amplifier 22 VrefL 11 10 24 1 SFOR MGE645 BOL BIL 3 7 SERIAL OUTPUT INTERFACE 8 9 OVLD SDO SWS SCK operational amplifier 23 VDDA HPEN TEST1 SLAVE Fig.1 Block diagram. 1998 Nov 17 3 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems PINNING SYMBOL SFOR PIN 1 DESCRIPTION SAA7367 TTL level input; in normal mode this input selects the serial interface output format; output format is selected as follows: SFOR = HIGH selects Format 1 SFOR = LOW selects Format 2 (similar to I2S) STDB 2 schmitt-trigger input; in normal mode, this input is used to select standby mode: STDB = HIGH selects normal operation STDB = LOW selects standby mode (low power consumption) OVLD 3 TTL level output; in normal mode this output indicates whether the internal digital signal is within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately 11 ms); in standby mode this output is forced LOW CMOS level input; system clock input; nominally clocked at 256fs digital supply voltage (4.5 to 5.5 V) digital ground TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in standby mode, this output is high impedance TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW), this pin outputs the serial interface word select signal; in slave mode (SLAVE = HIGH), this pin is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is always an input (high impedance); for polarity: see Table 1 TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the LOW-to-HIGH transition Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used to select extra serial interface formats (see Table 2) TTL level input; this input is used to enable the internal high-pass filter when HIGH; in scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as ‘scan chain c’ input Test B; CMOS level input with internal pull-up; in normal applications, this input should be left HIGH analog ground; this pin is internally connected to VSS via the on-chip substrate contacts current reference generator output; 33 k Ω in parallel with 22 nF.


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