IS42S81600A

IS42S81600A, IS42LS81600A IS42S16800A, IS42LS16800A IS42S32400A, IS42LS32400A 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM FEATURES Clock frequency: 133 100, MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power supply IS42LS81600A IS42LS16800A IS42LS32400A IS42S81600A IS42S16800A IS42S32400A LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Extended Mode Register Programmable Power Reduction Feature by partial array activation during Self-Refresh Auto Refresh (CBR) Temp. Compensated Self Refresh. Self Refresh with programmable refresh periods 4096 refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Industrial Temperature Availability VDDQ VDD 2.5V 1.8V (2.5V tolerant) 2.5V 1.8V (2.5V tolerant) 2.5V 1.8V (2.5V tolerant) 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V IS42LS81600A IS42S81600A 4M x8x4 Banks 54pin TSOPII ISSI ® ADVANCED INFORMATION AUGUST 2002 OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDARM is organized as follows. IS42LS16800A IS42S16800A 2M x16x4 Banks 54ball FBGA 54 pin TSOP...