CY2XP21

PRELIMINARY CY2XP21 125 MHz LVPECL Clock Generator Features ■ ■ ■ ■ ■ ■ ■ Functional Description The CY2XP21 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate a 125 MHz clock, which is ideal for 10 Gb Ethernet applications. It also produces an output frequency that is five times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP21 has a crystal oscillator interface input and one LVPECL output pair. One LVPECL Output Pair Output Frequency: 112 MHz to 140 MHz External Crystal Frequency: 22.4 MHz to 28 MHz Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal (1.875 MHz to 20 MHz): 0.4 ps (Typical) Pb-free 8-Pin TSSOP Package Supply Voltage: 3.3V or 2.5V Commercial and Industrial Temperature Ranges Logic Block Diagram XIN External Crystal XOUT CRYSTAL OSCILLATOR LOW -N OISE PLL OUTPUT DIVIDER CLK CLK# Pinouts Figure 1. Pin Diagram - 8-Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# NC Table 1. Pin Definition - 8-Pin TSSOP Pin Number 1, 8 2 3, 4 5 6,7 Pin Name VDD VSS XOUT, XIN NC CLK#, CLK LVPECL output Power Power XTAL output and input I/O Type 3.3V or 2.5V power supply Ground Parallel resonant crystal interface No Connect Differential Clock Output Description www.DataSheet4U.net Cypress Semiconductor Corporation Document #: 001-52849 Rev. *A 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised June 15, 2009 [+] F...