Bus Buffer Gate
HD74LV1GT126A
Bus Buffer Gate with 3–state Output / CMOS Logic Level Shifter
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REJ03D0124-0900 Rev.9....
Description
HD74LV1GT126A
Bus Buffer Gate with 3–state Output / CMOS Logic Level Shifter
www.DataSheet4U.net
REJ03D0124-0900 Rev.9.00 Mar 21, 2008
Description
The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and highspeed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series. Supplied on emboss taping for high-speed automatic mounting. TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : –40 to +85°C Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V) All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z) Output current ±6 mA...
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