MPC5645B

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5646C Rev. 3, May 2011 MPC5646C MPC5646C Microcontroller Data Sheet e200z4d dual issue, 32-bit core Power Architecture compliant CPU – Up to 120 MHz – 4 KB, 2/4-Way Set Associative Instruction Cache – Variable length encoding (VLE) – Embedded floating-point (FPU) unit www.DataSheet4U.net – Supports Nexus3+ e200z0h single issue, 32-bit core Power Architecture compliant CPU – Up to 80 MHz – Variable length encoding (VLE) – Supports Nexus3+ Up to 3 MB on-chip flash memory: flash page buffers to improve access time Up to 256 KB on-chip SRAM 64 KB on-chip data flash memory to support EEPROM emulation Up to 16 semaphores across all slave ports User selectable MBIST Low-power modes supported: STOP, HALT, STANDBY 16 region Memory Protection Unit (MPU) Dual-core Interrupt Controller (INTC). Interrupt sources can be routed to e200z4d, e200z0h, or both Frequency-Modulated Phase-Locked Loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, flash memory, and SRAM from multiple bus masters 32 channel eDMA controller with DMAMUX Timer supports input/output channels providing 16-bit input capture, output compare, and PWM functions (eMIOS) 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit Cross Trigger Unit (CTU) to enable synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Up to 8 serial peripheral interface (...