MPC5646C

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5646C Rev.6, 02/2014 MPC5646C Microcontroller Data Sheet On-chip modules available within the family include the following features: e200z4d dual issue, 32-bit core Power Architecture compliant CPU — Up to 120 MHz — 4 KB, 2/4-Way Set Associative Instruction Cache — Variable length encoding (VLE) — Embedded floating-point (FPU) unit — Supports Nexus3+ e200z0h single issue, 32-bit core Power Architecture compliant CPU — Up to 80 MHz — Variable length encoding (VLE) — Supports Nexus3+ Up to 3 MB on-chip flash memory: flash page buffers to improve access time Up to 256 KB on-chip SRAM 64 KB on-chip data flash memory to support EEPROM emulation Up to 16 semaphores across all slave ports User selectable MBIST Low-power modes supported: STOP, HALT, STANDBY 16 region Memory Protection Unit (MPU) Dual-core Interrupt Controller (INTC). Interrupt sources can be ...