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IDT72V3686 Dataheets PDF



Part Number IDT72V3686
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3 VOLT CMOS TRIPLE BUS SyncFIFO
Datasheet IDT72V3686 DatasheetIDT72V3686 Datasheet (PDF)

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2 IDT72V3686 IDT72V3696 IDT72V36106 • • • • • • • FEATURES • • • • • • Memory storage capacity: IDT72V3686 – 16,384 x 36 x 2 IDT72V3696 – 32,768 x 36 x 2 IDT72V36106 – 65,536 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 18-bit (wor.

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3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2 IDT72V3686 IDT72V3696 IDT72V36106 • • • • • • • FEATURES • • • • • • Memory storage capacity: IDT72V3686 – 16,384 x 36 x 2 IDT72V3696 – 32,768 x 36 x 2 IDT72V36106 – 65,536 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1024) • • • • Serial or parallel programming of partial flags Big- or Little-Endian format for word and byte bus sizes Loopback mode on Port A Retransmit Capability Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA, CLKB and CLKC may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin compatible to the lower density parts, IDT72V3626/72V3636/ 72V3646/72V3656/72V3666/72V3676 Industrial temperature range (–40° C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 CLKA CSA W/RA ENA MBA LOOP MRS1 PRS1 Mail 1 Register Output BusMatching Output Register Input Register Port-A Control Logic 18 B0-B17 36 RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 36 FIFO1, Mail1 Reset Logic 36 Port-B Control Logic Write Pointer Read Pointer CLKB RENB CSB MBB SIZEB FFA/IRA AFA FS2 FS0/SD FS1/SEN A0-A35 EFA/ORA AEA FIFO1 Status Flag Logic Common Port Control Logic (B and C) EFB/ORB AEB Programmable Flag Offset Registers 16 FIFO2 Timing Mode BE Status Flag Logic Read Pointer Write Pointer FIFO2, Mail2 Reset Logic Input BusMatching Input Register 18 FWFT FFC/IRC AFC MRS2 PRS2 36 RT1 RTM RT2 Output Register FIFO1 and FIFO2 Retransmit Logic 36 RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 Mail 2 Register 36 C0-C17 CLKC WENC MBC SIZEC 4676 drw01 Port-C Control Logic MBF2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. www.DataSheet4U.net COMMERICAL TEMPERATURE RANGE  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2003 1 DSC-4676/4 IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36 COMMERCIAL TEMPERATURE RANGE DESCRIPTION The IDT72V3686/72V3696/72V36106 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic, high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be read out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or PIN CONFIGURATION CSA FFA/IRA EFA/ORA PRS1/RT1 VCC AFA AEA MBF2 MBA MRS1 FS0/SD CLKC GND FS1/SEN MRS2 MBB MBF1 VCC AEB AFC EFB/ORB FFC/IRC GND CSB WENC RENB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 INDEX A9 A8 A7 A6 GND A5 A4 A3 FS2 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 W/RA ENA CLKA GND A35 A34 A33 A32 Vcc A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/FWFT GND A22 Vcc A21 A20 A19 A18 GND A17 A16 A15 A14 A13 Vcc A12 GND A11 A10 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 CLKB PRS2/RT2 LOOP C17 C16 C15 C14 RTM MBC C13 C12 C11 C10 C9 C8 VCC C7 C6 SIZEB GND C5 C4 C3 C2 C1 C0 GND B17 B16 SIZEC VCC B15 B14 B13 B12 GND B11 B10 4676 drw02 TQFP (PK128-1, order code: PF) TOP VIEW 2 IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,3.


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