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U440 Dataheets PDF



Part Number U440
Manufacturers Micross
Logo Micross
Description Low Leakage
Datasheet U440 DatasheetU440 Datasheet (PDF)

U440 MONOLITHIC DUAL N-CHANNEL JFET Linear Systems replaces discontinued Siliconix U440 The U440 is a tightly matched Monolithic Dual N-Channel JFET The U440 are monolithic dual JFETs mounted in a single TO-71 package. The monolithic dual chip design reduces parasitics and gives better performance at very high frequencies while ensuring extremely tight matching. These devices are an excellent choice for use as wideband differential amplifiers in demanding test and measurement applications. The .

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U440 MONOLITHIC DUAL N-CHANNEL JFET Linear Systems replaces discontinued Siliconix U440 The U440 is a tightly matched Monolithic Dual N-Channel JFET The U440 are monolithic dual JFETs mounted in a single TO-71 package. The monolithic dual chip design reduces parasitics and gives better performance at very high frequencies while ensuring extremely tight matching. These devices are an excellent choice for use as wideband differential amplifiers in demanding test and measurement applications. The U440 is a direct replacement for discontinued Siliconix U440. The hermetically sealed TO-71 is well suited for military applications. (See Packaging Information). U440 Applications: ƒ Wideband Differential Amps ƒ High-Speed,Temp-Compensated SingleEnded Input Amps ƒ High-Speed Comparators ƒ Impedance Converters and vibrations detectors. MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)  SYMBOL  CHARACTERISTIC  |VGS1 – VGS2 |  Differential Gate to Source Cutoff Voltage  ∆|VGS1 – VGS2 | / ∆T  Differential Gate to Source Cutoff     Voltage Change with Temperature  IDSS1  / IDSS2  Gate to Source Saturation Current Ratio    Gfs1 / Gfs2  Forward Transconductance Ratio2    FEATURES  Direct Replacement for SILICONIX U440  HIGH CMRR  LOW GATE LEAKAGE  ABSOLUTE MAXIMUM RATINGS 1  @ 25°C (unless otherwise noted)  Maximum Temperatures  Storage Temperature  Operating Junction Temperature  Maximum Power Dissipation  Continuous Power Dissipation (Total)  Maximum Currents  Gate Current  Maximum Voltages  Gate to Drain  Gate to Source  Gate to Gate          MIN        TYP  20  MAX  10      UNITS  mV  µV/°C  %  CMRR ≥ 85dB  IGSS ≤ 1 pA  ‐65°C to +150°C  ‐55°C to +135°C  500mW  50mA  ‐25V  ‐25V  ±50V          CONDITIONS  VDG = 10V, ID = 5mA            VDG = 10V, ID = 5mA       TA = ‐55°C to +125°C  VDS = 10V, VGS = 0V  CMRR  Click To Buy   0.07    0.97  85    %  Common Mode Rejection Ratio      dB  TYP.    ‐3.5  15  ‐1  ‐1  6  70  3  1  4  MAX.    ‐6  30  ‐500  ‐500  9  200        UNITS  V  V  mA  pA  pA  mS  µS  pF  pF  nV/√Hz  CONDITIONS  IG = ‐1µA, VDS = 0V  VDS = 10V, ID = 1nA  VDS = 10V, VGS = 0V  VGS = ‐15V, VDS = 0V  VDG = 10V, ID = 5mA  Forward Transconductance  Output Conductance  Input Capacitance  Reverse Transfer Capacitance  Equivalent Input Noise Voltage  4.5          TO-71 (Top View) VDS = 10V, ID = 5mA, f = 1kHz  VDG = 5 to 10V, ID = 5mA             ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL  CHARACTERISTICS  MIN.  BVGSS  Gate to Source Breakdown Voltage  ‐25  VGS(off)  Gate to Source Cutoff Voltage  ‐1  IDSS  Gate to Source Saturation Current  6  IGSS  Gate Leakage Current3    IG  Gate Operating Current    gfs  gos  CISS  CRSS  en  VDS = 10V, ID= 5mA, f = 1kHz  VDS = 10V, ID = 5mA, f = 1MHz  VDS = 10V, ID = 5mA, f = 10kHz  Notes:  1. Absolute Maximum ratings are limiting values above which serviceability may be impaired 2. Pulse Test: PW ≤ 300µs Duty Cycle ≤ 3%  3. Assumes smaller value in numerator  Available Packages: U440 in TO-71 U440 available as bare die Please contact Micross for full package and die dimensions: Email: [email protected] www.DataSheet4U.com Web: www.micross.com/distribution.aspx Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. .


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