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HY57V281620FLTP Dataheets PDF



Part Number HY57V281620FLTP
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description Synchronous DRAM Memory 128Mbit (8Mx16bit)
Datasheet HY57V281620FLTP DatasheetHY57V281620FLTP Datasheet (PDF)

128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 1.0 1.1 Initial Draft Final Version Correct Typo Error Page10, Page12 Correct Typo Error Page 10 : The Note for the Parameter “tOH” ( 2 -> Blank ) History Draft Date Jan. 2007 Apr. 2007 July. 2007 Remark Preliminary 1.2 Oct. 2007 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any r.

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Document
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 1.0 1.1 Initial Draft Final Version Correct Typo Error Page10, Page12 Correct Typo Error Page 10 : The Note for the Parameter “tOH” ( 2 -> Blank ) History Draft Date Jan. 2007 Apr. 2007 July. 2007 Remark Preliminary 1.2 Oct. 2007 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Oct. 2007 1 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620F(L/S)TP Series DESCRIPTION The Hynix HY57V281620F(L/S)TP series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V281620F(L/S)T(P) series is organized as 4banks of 2,097,152 x 16. HY57V281620F(L/S)TP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES • • • • Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM • • • • Internal four banks operation Auto refresh and self refresh 4096 Refresh cycles / 64ms - Commercial Temperature (0oC to 70oC) - Industrial Temperature (-40oC to 85oC) Operating Temperature • • • • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency; 2, 3 Clocks Burst Read Single Write operation ORDERING INFORMATION Part No. HY57V281620F(L/S)TP-5 HY57V281620F(L/S)TP-6 HY57V281620F(L/S)TP-7 HY57V281620F(L/S)TP-H Note: 1. HY57V281620FTP Series: Normal power, Lead Free. 2. HY57V281620FLTP Series: Low power, Lead Free. 3. HY57V281620FLTP Series: Super Low power, Lead Free. 4. HY57V281620FST(P) Series: Super Low power; Contact Hynix for availability 5. HY57V281620F(L/S)T(P)-x: Commercial Temperature (0oC to 70oC) 6. HY57V281620F(L/S)T(P)-xI: Industrial Temperature (-40oC to 85oC) Clock Frequency 200MHz 166MHz 143MHz 133MHz Organization Interface Package 4Banks x 2Mbits x16 LVTTL 54 Pin TSOPII Rev. .


HY57V281620FTP HY57V281620FLTP HY57V281620FSTP


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