K7P401823B

K7P403623B K7P401823B Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM 128Kx36 & 256Kx18 SRAM Revision History Rev. No. Rev. 0.0 Rev. 0.1 History - Preliminary specification release - Update DC CHARACTERISTICS x36 : IDD6 : TBD -> 300, IDD65 -> 290, IDD7 -> 280. x18 : IDD6 : TBD -> 290, IDD65 -> 280, IDD7 -> 270. - Change simbol in DC CHARACTERISTICS IDD6, IDD65, IDD7 -> IDD65, IDD70, IDD75 - Final Version - Add Single ended differential clock on clock comment. Draft Date Oct. 2002 Jan. 2003 Remark Preliminary Preliminary Feb. 2003 Rev. 0.2 Preliminary Rev. 1.0 Rev. 1.1 Jun. 2003 Jun. 2003 Final Final www.DataSheet4U.com The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters. -1- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM 128Kx36 & 256Kx18 Synchronous Pipelined SRAM FEATURES 128Kx36 or 256Kx18 Organizations. 3.3V VDD, 2.5/3.3V VDDQ. LVTTL 2.5/3.3V Input and Output Levels. Differential, PECL clock / Single ended or differential LVTTL clock Inputs Synchronous Read and Write Operation Registered Input and Latched Output Internal Pipeline Latches to Support Late Write. Byte Write Capability(four...