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K7D321874C Dataheets PDF



Part Number K7D321874C
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 1Mx36 & 2Mx18 SRAM
Datasheet K7D321874C DatasheetK7D321874C Datasheet (PDF)

K7D323674C K7D321874C 1Mx36 & 2Mx18 SRAM 36Mb DDR SRAM Specification 153BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR.

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K7D323674C K7D321874C 1Mx36 & 2Mx18 SRAM 36Mb DDR SRAM Specification 153BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. www.DataSheet4U.com * Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 August 2006 K7D323674C K7D321874C Document Title 36M DDR SYNCHRONOUS SRAM 1Mx36 & 2Mx18 SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 Rev. 1.0 History Initial document. Change AC Characteritics, Pin Capacitance, DC Characteristics Change Samsung JEDEC Code in ID REGISTER DEFINITION Correct Typo Draft Data Nov. 2005 Apr. 2006 Jun. 2006 Aug. 2006 Remark Advance Preliminary Preliminary Final www.DataSheet4U.com -2- Rev. 1.0 August 2006 K7D323674C K7D321874C FEATURES • • • • • 1Mx36 or 2Mx18 Organizations. 1.8~2.5V VDD/1.5V ~1.8VDDQ. HSTL Input and Outputs. Single Differential HSTL Clock. Synchronous Pipeline Mode of Operation with Self-Timed Late Write. • Free Running Active High and Active Low Echo Clock Output Pin. • Registered Addresses, Burst Control and Data Inputs. 1Mx36 & 2Mx18 SRAM • Registered Outputs. • Double and Single Data Rate Burst Read and Write. • Burst Count Controllable With Max Burst Length of 4 • Interleaved and Linear Burst mode support • Bypass Operation Support • Programmable Impedance Output Drivers. • JTAG Boundary Scan (subset of IEEE std. 1149.1) • 153(9x17) Ball Grid Array Package(14mmx22mm) • No Output enable support. GENERAL DESCRIPTION The K7D323674C and K7D321874C are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 1,048,576 words by 36 bits for K7D323674C and 2,097,152 words by 18 bits for K7D321874C, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and falling edge of K clock for a double data rate (DDR) write operations. Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access time for all SDR and DDR operations. The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm pitch. ORDERING INFORMATION Organization 1Mx36 Maximum Frequency 400MHz 375MHz 333MHz 400MHz 2Mx18 375MHz 333MHz Part Number K7D323674C-H(G)1C40 K7D323674C-H(G)1C37 K7D323674C-H(G)1C33 K7D321874C-H(G)1C40 K7D321874C-H(G)1C37 K7D321874C-H(G)1C33 Note 1. H(G) [Package type] : G-Pb Free, H-Pb www.DataSheet4U.com -3- Rev. 1.0 August 2006 K7D323674C K7D321874C FUNCTIONAL BLOCK DIAGRAM SA[0:20]( or SA[0:21]) Address Register CE 20(or 21) 18(or 19) (Burst Address) Burst Counter (Burst Write Address) 20(or 21) 18(or 19) 2:1 MUX 1Mx36 & 2Mx18 SRAM Dec. Data Out K,K Clock Buffer Memory Array 1Mx36 or (2Mx18) Data In 36(or18)x2 W/D Array 36(or18)x2 Write Buffer Comparator B1 B3 Advance Co Control SD/DD Write Address Register (2 stage) CE Synchronous Select & R/W control CE R/W LD Internal Clock Generator Data Output Strobe Data Output Enable State Machine Strobe_out 36(or 18)x2 S/A Array 36(or 18)x2 2 : 1 MUX B2 Output Buffer Echo Clock Output Data In Register (2 stage) 36(or 18) DQ CQ,CQ XDIN PIN DESCRIPTION Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 LBO ZQ Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable Single/Double Data Selection Linear Burst Order Output Driver Impedance Control Input Pin Name TCK TMS TDI TDO VREF VDD VDDQ VSS NC Pin Description JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output HSTL I.


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