Document
K4S560432J K4S560832J K4S561632J
Synchronous DRAM
256Mb J-die SDRAM Specification
54 TSOP-II with Lead-Free & Halogen-Free
(RoHS compliant)
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Rev. 1.22 August 2008
K4S560432J K4S560832J K4S561632J
Synchronous DRAM
Table of Contents
1.0 Features ....................................................................................................................................... 4 2.0 General Description ................................................................................................................... 4 3.0 Ordering Information .................................................................................................................. 4 4.0 Package Physical Dimension ................................................................................................... 5 5.0 Functional Block Diagram......................................................................................................... 6 6.0 Pin Configuration (Top view) ..................................................................................................... 7 7.0 Pin Function Description ........................................................................................................... 7 8.0 Absolute Maximum Ratings........................................................................................................8 9.0 DC Operating Conditions ........................................................................................................... 8 10.0 Capacitance............................................................................................................................... 8 11.0 DC Characteristics (x4, x8) ......................................................................................................9 12.0 DC Characteristics (x16) ........................................................................................................10 13.0 AC Operating Test Conditions ...............................................................................................11 14.0 Operating AC Parameter ........................................................................................................11 15.0 AC Characteristics ..................................................................................................................12 16.0 DQ Buffer Output Drive Characteristics ...............................................................................12 17.0 IBIS Specification .....................................................................................................................13 18.0 Simplified Truth Table ............................................................................................................15
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Rev. 1.22 August 2008
K4S560432J K4S560832J K4S561632J
Synchronous DRAM
Month June October January March August Year 2007 2007 2008 2008 2008 - Release 1.0 version SPEC - Changed IDD current SPEC - Revised typo of package dimension - Added the comment of Halogen-free supporting - Added 200Mhz speed - Added Package pin out lead width - Added 200MHz current SPEC - Corrected font format History
Revision History
Revision 1.0 1.1 1.2 1.21 1.22
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3 of 15
Rev. 1.22 August 2008
K4S560432J K4S560832J K4S561632J
Synchronous DRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM 1.0 Features
• • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (8K Cycle) Lead-Free & Halogen-Free Package RoHS compliant
• • • • • • •
2.0 General Description
The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as.