DatasheetsPDF.com
CY7C1245KV18
36-Mbit QDR II SRAM 4-Word Burst Architecture
Description
36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 ® Features ■ Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18 – 4 M × 8 CY7C1256KV18 – 4 M × 9 CY7C1243KV18 – 2 M × 18 CY7C1245KV18 – 1 M × ...
Cypress Semiconductor
Download CY7C1245KV18 Datasheet
Similar Datasheet
CY7C1245KV18
36-Mbit QDR II SRAM 4-Word Burst Architecture
- Cypress Semiconductor
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (
Privacy Policy & Contact
)
